Ms. Irene Shi Profile

KEYWORDS: Photomasks, Critical dimension metrology, Semiconducting wafers, Integrated circuits, Electron beams, Transistors, Performance modeling, Semiconductors, Integrated circuit design, Product engineering

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Proceedings Article | 19 March 2015 Paper

Overlay improvement by exposure map based mask registration optimization

Irene Shi, Eric Guo, Ming Chen, Max Lu, Gordon Li, Rivan Li, Eric Tian

Proceedings Volume 9424, 942413 (2015) https://doi.org/10.1117/12.2084958

KEYWORDS: Photomasks, Image registration, Overlay metrology, Lithography, Semiconducting wafers, Process control, Error analysis, Double patterning technology, Data modeling, Semiconductors

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Along with the increased miniaturization of semiconductor electronic devices, the design rules of advanced semiconductor devices shrink dramatically. [1] One of the main challenges of lithography step is the layer-to-layer overlay control. Furthermore, DPT (Double Patterning Technology) has been adapted for the advanced technology node like 28nm and 14nm, corresponding overlay budget becomes even tighter. [2][3] After the in-die mask registration (pattern placement) measurement is introduced, with the model analysis of a KLA SOV (sources of variation) tool, it’s observed that registration difference between masks is a significant error source of wafer layer-to-layer overlay at 28nm process. [4][5] Mask registration optimization would highly improve wafer overlay performance accordingly. It was reported that a laser based registration control (RegC) process could be applied after the pattern generation or after pellicle mounting and allowed fine tuning of the mask registration. [6]

In this paper we propose a novel method of mask registration correction, which can be applied before mask writing based on mask exposure map, considering the factors of mask chip layout, writing sequence, and pattern density distribution. Our experiment data show if pattern density on the mask keeps at a low level, in-die mask registration residue error in 3sigma could be always under 5nm whatever blank type and related writer POSCOR (position correction) file was applied; it proves random error induced by material or equipment would occupy relatively fixed error budget as an error source of mask registration. On the real production, comparing the mask registration difference through critical production layers, it could be revealed that registration residue error of line space layers with higher pattern density is always much larger than the one of contact hole layers with lower pattern density. Additionally, the mask registration difference between layers with similar pattern density could also achieve under 5nm performance. We assume mask registration excluding random error is mostly induced by charge accumulation during mask writing, which may be calculated from surrounding exposed pattern density. Multi-loading test mask registration result shows that with x direction writing sequence, mask registration behavior in x direction is mainly related to sequence direction, but mask registration in y direction would be highly impacted by pattern density distribution map. It proves part of mask registration error is due to charge issue from nearby environment. If exposure sequence is chip by chip for normal multi chip layout case, mask registration of both x and y direction would be impacted analogously, which has also been proved by real data. Therefore, we try to set up a simple model to predict the mask registration error based on mask exposure map, and correct it with the given POSCOR (position correction) file for advanced mask writing if needed.

Proceedings Article | 8 October 2014 Paper

The defect printability study for 28nm mode mask

Catherine Ren, Eric Guo, Irene Shi, Eric Tian

Proceedings Volume 9235, 923523 (2014) https://doi.org/10.1117/12.2066099

KEYWORDS: Photomasks, Semiconducting wafers, Inspection, Scanners, Critical dimension metrology, Defect inspection, Defect detection, Image processing, Lithography, Polarization

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Proceedings Article | 9 September 2013 Paper

Phase preservation study on ArF mask for haze-free mask resist strip and cleaning

Irene Shi, Eric Guo, Eric Tian, Tracy Gu, Forrest Jiang, Sandy Qian, Daisuke Matsushima, Jinyuan Pang

Proceedings Volume 8880, 88801L (2013) https://doi.org/10.1117/12.2023019

KEYWORDS: Oxygen, Photoresist processing, Photomasks, Plasma, Phase shifts, Ultraviolet radiation, Etching, SRAF, Dry etching, Oxidation

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Proceedings Article | 10 April 2013 Paper

Enhanced photomask quality control by 2D structures monitoring using auto image-to-layout method on advanced 28nm technology node or beyond

Eric Guo, Irene Shi, Eric Tian, Chingyun Hsiang, Guojie Cheng, Li Ling, Shijie Chen, Ye Chen, Ke Zhou, Joanne Wu, KeChih Wu

Proceedings Volume 8681, 86810Y (2013) https://doi.org/10.1117/12.2009030

KEYWORDS: Photomasks, Semiconducting wafers, Scanning electron microscopy, Mask making, Databases, Image quality, Source mask optimization, Image processing, Semiconductors, Lithography

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As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) [1]. Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D [2] [3] [4] only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) [6].

Proceedings Article | 14 October 2011 Paper

Simulation based mask defect printability verification and disposition. Part II

Eric Guo, Irene Shi, Blade Gao, Nancy Fan, Guojie Cheng, Li Ling, Ke Zhou, Gary Zhang, Ye Chen, Chingyun Hsiang, Bo Su

Proceedings Volume 8166, 81662D (2011) https://doi.org/10.1117/12.896879

KEYWORDS: Photomasks, Scanning electron microscopy, Image processing, Wafer-level optics, Semiconducting wafers, Lithography, Inspection, Process modeling, Optical inspection, Software development

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We have reported the first part of the work in 2009 BACUS meeting [1], using primarily SEM mask defect images as input. This paper is the extension of that work using mask optical inspection images with a new image process algorithm. Simulation has been widely used in overall lithography process, called computational lithography, as an effective way for cost and time reduction. As the industry moves towards 45nm and 32nm technology nodes in production, the mask inspection, with increased sensitivity and shrinking critical defect size, catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post inspection defect classification and disposition: which defects are real defects, and among the real defects, which defects should be repaired and how to verify the post-repair defects. In this paper, we report simulation mask defect printability check and disposition results extending beyond SEM mask defect images [1] into optical inspection mask defects images to demonstrate cost and time reduction by simulation in mask defect management area. A new algorithm has been developed in the software tool to convert optical inspection mask defect images into "pseudo-defect" polygons in GDS format. Then, the converted defect polygons were filled with the correct tone to form mask patterns and were merged back into the original design GDS. With lithography process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be simulated. If such complicated model is not available, a simple optical model can be used to get aerial image intensity of AOI. With build-in contour analysis functions, the software can easily compare the contour (or intensity) differences between real mask (with defect) and normal mask (without defect). With user provided judging criteria, software can be easily disposition the defect based on contour comparison. The software has been tested and adapted for production use. We will present some accuracy test results against AIMS tool or wafer CDs in defect printability check.

Proceedings Article | 11 May 2009 Paper

Mask and wafer evaluation of Sigma7500 pattern generator applied to 65nm logic metal and via layers

Frank Liu, Irene Shi, Qingwei Liu, Likeit Zhu, Shirley Zhao, Eric Guo

Proceedings Volume 7379, 737919 (2009) https://doi.org/10.1117/12.824286

KEYWORDS: Photomasks, Optical proximity correction, Semiconducting wafers, Binary data, Vestigial sideband modulation, Critical dimension metrology, Logic, Metals, Deep ultraviolet, Lithography

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