As semiconductor devices become extremely integrated and their geometry continues to shrink, even slight critical dimension (CD) move or phase decay during photomask cleaning may have a negative impact on the CD uniformity performance of photomask. In addition, the printing of sub-resolution assist-features (SRAF) on photomask becomes the main limiting factor in using high power and low frequency Mega-sonic cleaning process, therefore, the balance between SRAF damage and clean performance becomes extremely important. In this research, the CD movement both on Chrome layer and MoSi layer and the phase and transmission decay on MoSi layer of advanced PSM photomask induced by Tetra-Methyl-Ammonium-Hydroxide (TMAH) based cleaning process were studied. Meanwhile, the difference between TMAH and SC1 were emphasized. The results showed that TMAH has significant advantage in CD move and phase decay. We also researched the SRAF damage condition after cleaning by the chemical of TMAH with Multi-Beam and Multi-Frequency (MBMF) mode. In addition, we collected different kinds of particles to study the particle remove capability of TMAH under MBMF mode.
OMOG (opaque MoSi on glass) blank is widely used in advanced masks because of its advantage in high resolution and 3D effect1-2. And the manufacture flow is simple compared to phase shift mask. But the repair of this type mask is a challenge. The OMOG material is sensitive to the etching gas thus the etching rate is much higher than PSM. This article presents a problem, the poor edge roughness after repair in OMOG mask, is also related to the high etching rate. The CD (critical dimension) of advanced masks is very small. If there is some distortion in the features’ edge, the AIMS result is easy out of spec. The poor edge roughness we met usually gets poor AIMS result. To find the reason, we checked the manufacture flow and then focused on three steps: repair process, plasma treated process and short clean. Finally we found the plasma treated process was the main reason, and the clean process also contributed to it. Plasma process makes the mask surface oxidization and the oxide layer is high clean durability. The etching rate of oxide is slower than pure OMOG material, and the oxide layer’s uniformity is not good. The two characteristics lead to different etching ratio in the defect area. This is the reason of the poor edge roughness. If the oxide layer is uniform in the defect area, the problem won’t happen. That’s why not all the masks we repaired met the problem. We also found the removal of the oxide layer by clean process could solve this problem. This is an indirect evidence for explaining the reason.
To deliver a defect-free photomask, is an essential step of mask manufacturing. EB (Electron-beam) repair is widely applied to deal with defects on photomasks, and has to cover etch and deposition capabilities without any pattern damage. However, mask repair is facing more challenges, with the shrinkage of minimum feature resolution for advanced technology nodes. Especially for micro defects at the edge of wafer printability specifications, differences between defect and reference may be tiny and hard to distinguish in visual or by existing methods on repair tools, so that it was difficult to start. <p> </p>In this paper, a new approach named Contour-based 2D Metrology will be introduced as assistance for the repair processes of such challenging micro defects. Both CDSEM images of defect and reference are input for extracting; then contour-based patterns are overlapped for each other and compared with GDS as well, to describe quantitative differences for each micro area. Assisted with such rigorous and comprehensive data analysis, micro defects can be accurately positioned according to Aims Results and repair processes would be proceeding.
One of the key challenges of photomask manufacture is to achieve defect-free masks. Clean and repair has been applied
to manage defects and particles on the mask imported during manufacturing processes. Since photomask patterns
become smaller and more complicated as integrated circuit (IC) scaling to 28 nm node and below, the increasingly
importance of mask quality compels us continuously research on more effective defect treatment solutions, to achieve
mask yield enhancement and on-schedule delivery.
In this paper, we would like to introduce new approaches of defect management with dry treatment assistance, according
to particular defect types. One is using plasma etching gases of Cl2/O2 to change the properties of glue compounds
adhering to the mask surface, and make them removed by conventional cleaning. Another is the application of O2
plasma dry treatment for the benefit of alleviation on scan damage phenomenon, which comes from contamination on the
scan area due to excessive repair cycles.
Opaque Mosi on Glass (OMOG) photomask, significantly less prone to mask degradation, has been applied in leading-edge photolithographic flows on 20 nm and 14 nm node. Mask defect problem occurs at any time, rooted in various causes; therefore, defect printability disposition and verification need to be evaluated for new developing process. A series of programmed defects with typical sizes and shapes have been established for different mask patterns on OMOG masks and investigated for the defect printability influences through the CDSEM, AIMS and inspection tools. The results are compiled to produce the defect specifications that can be implemented on OMOG mask fabrication.
Critical Dimension (CD) Uniformity is one of the necessary parameters to assure good performance and reliable functionality of any integrated circuit (IC), and towards the advanced technology node 28nm and beyond, corresponding CD Uniformity becomes more and more crucial. It is found that bad mask CD Uniformity is a significant error source at 28nm process. The CD Uniformity on mask, if not controlled well, will badly impact wafer CD performance, and it has been well-studied that CD Uniformity issue from gate line-width in transistors would affect the device performance directly. In this paper we present a novel solution for mask global CD uniformity error correction, which is called as global loading effect correction (GLEC) method and applied nesting in the mask exposure map during the electron beam exposure. There are factors such as global chip layout, writing sequence and chip pattern density distribution (Global Loading), that work on the whole mask CD Uniformity, especially Global Loading is the key factor related to mask global CD error. From our experimental results, different pattern density distribution on mask significantly influenced the final mask CD Uniformity: the mask with undulating pattern density distribution provides much worse CD Uniformity than that with uniform one. Therefore, a GLEC model based on pattern density has been created to compensate the global error during the electron beam exposure, which has been proved to be efficacious to improve mask global CD Uniformity performance. Furthermore, it ’s also revealed that pattern type is another important impact factor, and GLEC coefficient need be modified due to the specific pattern type (e.g. dense line-space only, iso-space only or an average of them) to improve the corresponding mask CD uniformity.
Along with the increased miniaturization of semiconductor electronic devices, the design rules of advanced semiconductor devices shrink dramatically.  One of the main challenges of lithography step is the layer-to-layer overlay control. Furthermore, DPT (Double Patterning Technology) has been adapted for the advanced technology node like 28nm and 14nm, corresponding overlay budget becomes even tighter.  After the in-die mask registration (pattern placement) measurement is introduced, with the model analysis of a KLA SOV (sources of variation) tool, it’s observed that registration difference between masks is a significant error source of wafer layer-to-layer overlay at 28nm process.  Mask registration optimization would highly improve wafer overlay performance accordingly. It was reported that a laser based registration control (RegC) process could be applied after the pattern generation or after pellicle mounting and allowed fine tuning of the mask registration.  <p> </p>In this paper we propose a novel method of mask registration correction, which can be applied before mask writing based on mask exposure map, considering the factors of mask chip layout, writing sequence, and pattern density distribution. Our experiment data show if pattern density on the mask keeps at a low level, in-die mask registration residue error in 3sigma could be always under 5nm whatever blank type and related writer POSCOR (position correction) file was applied; it proves random error induced by material or equipment would occupy relatively fixed error budget as an error source of mask registration. On the real production, comparing the mask registration difference through critical production layers, it could be revealed that registration residue error of line space layers with higher pattern density is always much larger than the one of contact hole layers with lower pattern density. Additionally, the mask registration difference between layers with similar pattern density could also achieve under 5nm performance. We assume mask registration excluding random error is mostly induced by charge accumulation during mask writing, which may be calculated from surrounding exposed pattern density. Multi-loading test mask registration result shows that with x direction writing sequence, mask registration behavior in x direction is mainly related to sequence direction, but mask registration in y direction would be highly impacted by pattern density distribution map. It proves part of mask registration error is due to charge issue from nearby environment. If exposure sequence is chip by chip for normal multi chip layout case, mask registration of both x and y direction would be impacted analogously, which has also been proved by real data. Therefore, we try to set up a simple model to predict the mask registration error based on mask exposure map, and correct it with the given POSCOR (position correction) file for advanced mask writing if needed.
For the volume mask production of 28nm node and beyond, the defect disposition is an important factor for mask
process, due to the scaling feature sizes and advanced resolution enhancement technologies. In this paper, the series of
specifications for different mask patterns have been established from the defect printability study through the behaviors
of programmed defects with varies types and sizes on mask, AIMS and wafer. The defect disposition to qualify the mask
defects and verify the defect repair proceeds on the basis of the defect printability study. It is found that the defect
specification is an effective and industrialized approach for mask production.
Ozonated water, as an alternative to a Sulfuric – Peroxide Mixture (SPM), was introduced to the resist strip and cleaning
processes to prevent surface haze formation through the elimination of sulfuric acid from these processes.     
However, it also was found to cause significant change of optical characteristics and CD-linewidth shift on ArF6%
attenuation phaseshift masks (AttPSM). Although the use of 172nm Excimer UV light irradiation treatment before the
cleancouldimprove the above-mentioned shifts, after several clean cycle, this phase/CD preservation effect would be
dramatically degraded.  
In this paper, a novel approach of phase preservationto usedry treatments based on reactive plasma Asher as part of acid-free
resist strip or cleaning process is introduced.  We have investigated on the surface material integrity and CD stability
of MoSi based shifters and compared with above-mentioned approach of 172nm UV light irradiation treatment, and tried to
illustrate and explain the principle. Not only Asher process but also UV irradiation, is supposed to be kind of oxygen
activation process to accelerate oxidization on MoSi based shifter of ArF AttPSM masks, and created passivation layer
would stand out for wet cleaning; furthermore, plasma Asher process is in prior to UV irradiation. As shown in Cross-section
profiles on the masks without and with Asher process, although the deference is very limited, it may be proved that a thin
passivation layer was created on the surface and side of MoSi based shifter after Asher process.
As device features continue to shrink, achieving acceptable yields becomes increasingly challenging. In the photolithography process, mask error is one of the most critical error sources, since any imperfections on a mask will be amplified and transferred onto a wafer due to Mask Error Enhancement Factor (MEEF) . Furthermore, due to complexity of lithography optical proximity effect correction in advanced technology nodes, more and more 2D structures are applied into mask patterns. Furthermore, more 2D pattern configurations are susceptible to pattering failures due to their much high MEEF factor than 1D pattern. As a result, the conventional mask error control mechanisms for 1D    only, such as mean-to-target (MTT) and CD uniformity, are no longer adequate to deal with high MEEF 2D structures. In this paper, a novel 2D structure mask error monitoring technique is introduced to prevent fatal wafer printing errors such as CD error, line-end pull back and other pattern distortions to ensure high quality mask manufacturing and to improve wafer yield in advanced technology nodes. We will demonstrate the flow using typical 2D structure test patterns in 28nm technology node design or beyond. The SEM image would be taken and measured by this novel technique are used to monitor mask fidelity performance. This monitoring technique is based on Image-to-layout, as one of Anchor Semiconductor’s pattern centric techniques, which can extract contour and convert it into pattern layouts from SEM or optical image of masks. Further pattern signature analysis can be performed on the pattern (inner /outer vertex, space distance and edge distance), so that we can quickly identify target locations for 2D pattern measurements. We monitor the severity of 2D corner rounding on selected 28nm design rule masks by Pattern Fidelity (PF) ratio and correlate them with wafer printing results. 2D pattern measurement techniques and PF ratio monitoring system from SEM image is an effective approach to ensure high quality mask making in 28nm and advanced technology nodes. This PF ratio monitoring from 2D pattern SEM images is an effective approach to ensure high quality mask making in advanced 28nm node and beyond, which can overcome the inadequacy of current 1D measurement only method, especially for the masks are generated without source mask optimization (SMO) .
We have reported the first part of the work in 2009 BACUS meeting , using primarily SEM mask defect
images as input. This paper is the extension of that work using mask optical inspection images with a new
image process algorithm.
Simulation has been widely used in overall lithography process, called computational lithography, as an
effective way for cost and time reduction. As the industry moves towards 45nm and 32nm technology
nodes in production, the mask inspection, with increased sensitivity and shrinking critical defect size,
catches more and more nuisance and false defects. Increased defect counts pose great challenges in the post
inspection defect classification and disposition: which defects are real defects, and among the real defects,
which defects should be repaired and how to verify the post-repair defects. In this paper, we report
simulation mask defect printability check and disposition results extending beyond SEM mask defect
images  into optical inspection mask defects images to demonstrate cost and time reduction by
simulation in mask defect management area.
A new algorithm has been developed in the software tool to convert optical inspection mask defect images
into "pseudo-defect" polygons in GDS format. Then, the converted defect polygons were filled with the
correct tone to form mask patterns and were merged back into the original design GDS. With lithography
process model, the resist contour of area of interest (AOI-the area surrounding a mask defect) can be
simulated. If such complicated model is not available, a simple optical model can be used to get aerial
image intensity of AOI. With build-in contour analysis functions, the software can easily compare the
contour (or intensity) differences between real mask (with defect) and normal mask (without defect). With
user provided judging criteria, software can be easily disposition the defect based on contour comparison.
The software has been tested and adapted for production use. We will present some accuracy test results
against AIMS tool or wafer CDs in defect printability check.
As pattern density and OPC complexity grow, photomask write times on electron beam tools increase in proportion.
Reducing the write time would decrease mask-making costs, but the performance of any alternative mask writer must
meet all of the technical requirements on both mask and wafer. In addition, it is desirable to use existing OPC models in
order to avoid the costs of developing and maintaining separate OPC models for each writer. The Sigma7500 deep-UV
pattern generator provides the highest resolution available from a laser-based tool, and it has the advantage of
maintaining about a 3 hour write time even as the feature count increases.
In this study, the Sigma7500 and a variable shaped e-beam (VSB) tool are compared on 65nm metal1 and via1 layers.
In the first phase, the Sigma pattern positioning was matched to a SMIC reference grid and a registration value of
10 nm (3s) was achieved with scales removed. In the second phase, M1 and V1 masks were printed with both laser and
e-beam writers using the same pattern data and compared on CD uniformity, linearity and proximity. The Sigma7500
met all of the photomask requirements for these layers. The masks were then printed on wafers and the wafer data was
evaluated. The results were comparable to those for the e-beam masks and were within the requirements, indicating that
the Sigma7500 can handle these layers without the need to revise the e-beam mask OPC models.