Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
Extreme ultraviolet (EUV) lithography is one of the leading technologies for 16nm and smaller node device patterning.
One patterning issue intrinsic to EUV lithography is the shadowing effect due to oblique illumination at the mask and
mask absorber thickness. This effect can cause CD errors up to a few nanometers, consequently needs to be accounted
for in OPC modeling and compensated accordingly in mask synthesis. Because of the dependence on the reticle field
coordinates, shadowing effect is very different from the traditional optical and resist effects. It poses challenges to
modeling, compensation, and verification that were not encountered in tradition optical lithography mask synthesis.
In this paper, we present a systematic approach for shadowing effect modeling and model-based shadowing
compensation. Edge based shadowing effect calculation with reticle and scan information is presented. Model calibration
and mask synthesis flows are described. Numerical experiments are performed to demonstrate the effectiveness of the
EUV lithography is widely viewed as a main contending technology for 16nm node device patterning.
However, EUV has several complex patterning issues which will need accurate compensation in mask
synthesis development and production steps. The main issues are: high flare levels from optical element
roughness, long range flare scattering distances, large mask topography, non-centered illumination axis
leading to shadowing effects, new resist chemistries to model very accurately, and the need for full reticle
optical proximity correction (OPC). Compensation strategies for these effects must integrate together to
create final user flows which are easy to build and deploy with reasonable time and cost. Therefore,
accuracy, usability, speed and cost are important with methods that have considerably more complexity
than current optical lithography mask synthesis flows.
In this paper we analyze the state of the art in accurate prediction and compensation of several of these
complex EUV patterning issues, and compare that to 16nm node expected production needs. Next we
provide a description of integration issues and solutions which are being implemented for 16nm EUV
process development. This includes descriptions of OPC model calibration with flare, shadowing, and
topography effects. We also propose a realistic (in terms of accuracy and mask area) flare parameter calibration flow to improve short and longer range flare correction accuracy above what can be achieved with only a measured EUV flare PSF.
As semiconductor manufacturing moves to 32nm and 22nm technology nodes with 193nm water immersion
lithography, the demand for more accurate OPC modeling is unprecedented to accommodate the diminishing
process margin. Among all the challenges, modeling the process of Chemically Amplified Resist (CAR) is a
difficult and critical one to overcome. The difficulty lies in the fact that it is an extremely complex physical and
chemical process. Although there are well-studied CAR process models, those are usually developed for TCAD
rigorous lithography simulators, making them unsuitable for OPC simulation tasks in view of their full-chip
capability at an acceptable turn-around time. In our recent endeavors, a simplified reaction-diffusion model capable
of full-chip simulation was investigated for simulating the Post-Exposure-Bake (PEB) step in a CAR process. This
model uses aerial image intensity and background base concentration as inputs along with a small number of
parameters to account for the diffusion and quenching of acid and base in the resist film. It is appropriate for OPC
models with regards to speed, accuracy and experimental tuning. Based on wafer measurement data, the parameters
can be regressed to optimize model prediction accuracy. This method has been tested to model numerous CAR
processes with wafer measurement data sets. Model residual of 1nm RMS and superior resist edge contour
predictions have been observed. Analysis has shown that the so-obtained resist models are separable from the effects
of optical system, i.e., the calibrated resist model with one illumination condition can be carried to a process with
different illumination conditions. It is shown that the simplified CAR system has great potential of being applicable
to full-chip OPC simulation.
Low pass filtering of mask diffraction orders, in the projection tools used in microelectronics
industry, leads to a range of optical proximity effects, OPEs, impacting integrated circuit pattern
images. These predictable OPEs can be corrected with various, model-based optical proximity
correction methodologies, OPCs , the success of which strongly depends on the completeness of
the imaging models they use.
The image formation in scanners is driven by the illuminator settings and the projection lens
NA, and modified by the scanner engineering impacts due to: 1) the illuminator signature, i.e. the
distributions of illuminator field amplitude and phase, 2) the projection lens signatures
representing projection lens aberration residue and the flare, and 3) the reticle and the wafer scan
synchronization signatures. For 4x nm integrated circuits, these scanner impacts modify the
critical dimensions of the pattern images at the level comparable to the required image tolerances.
Therefore, to reach the required accuracy, the OPC models have to imbed the scanner illuminator,
projection lens, and synchronization signatures.
To study their effects on imaging, we set up imaging models without and with scanner
signatures, and we used them to predict OPEs and to conduct the OPC of a poly gate level of 4x
nm flash memory. This report presents analysis of the scanner signature impacts on OPEs and
OPCs of critical patterns in the flash memory gate levels.
Photolithography on reflective surfaces with topography can cause overexposure in some areas in the photoresist,
resulting in undesired critical dimension (CD) variations in the printed patterns. Using bottom anti-reflective coatings
(BARCs) will reduce the severity of the problem. However it is not a preferred solution in some situations due to added
process complexity, such as the case of implant blocking layer patterning. This topography proximity effect (TPE) has
been ignored in the mask synthesis flow for the 45nm and larger nodes due to its relatively small impact to the CDs.
When the device critical length reaches 32nm and lower, the variations on the implant layer caused by underlying
topography becomes more and more an issue and need to be addressed properly. In order to do that, simulation with nonplanar
stack is required. The available tools for photolithography simulation with wafer topography, such as Synopsys'
Sentaurus Lithography (S-Litho), usually adopt a rigorous approach based on the solution of the Maxwell equations and
unsuitable for full chip optical proximity correction (OPC) due to their prohibitively long runtimes. A fast method for
TPE modeling is needed to make full chip TPE correction feasible.
In this paper, we propose a computationally fast approximate method that captures TPE well. It enables fast model
calibration and full chip implant layer mask correction, and fits in the current OPC flows easily. We validate the
method's effectiveness by comparing its simulation results with those produced by Sentaurus Lithography. We also
show how it helps implant layer mask synthesis that takes TPE from previous layers into consideration.
In previous OPC model calibrations, most of the work was focused on how to calibrate a model for the best process
conditions. With process tolerance decreasing in coming lithography generations, it is increasingly important to be able
to predict pattern behavior through process window. Due to a low k1 factor that leads to a smaller process window, the
use of process window models is required for both optical proximity correction (OPC) and Lithography Rule Check
(LRC) applications to insure silicon success.
In this paper, we would try to calibrate multiple process window models. The resulting models will be verified and
judged using additional measurement data to demonstrate the quality.
In photo process development, simulation plays a very important role to optimize the photo condition prior to exposure wafers. In this report we would address a systematic methodology to accelerate the photo condition optimization through simulation with the aids of statistical methods. Moreover, this systematic methodology could also be used in any experiment design and emerges as a feasibility of automatic process optimization.