Thermal imaging is widely used in military applications. The current sensor technology updates make it possible to use on commercial products as well. The quality of the image is significantly important for the final product performance in the field. The main parameters that affect the quality are the sensor resolution, the optical performance and the image processing capability at the final stage. Even though improving final system performance requires development of the optical and the sensor systems, such hardware developments may become a challenging issue for many cases. At that time, FPGA based image processing on the final stage becomes crucial. The noise reduction, the contrast correction and the image optimization can be controlled by the FPGA based image processing techniques. In this study, possible techniques to remove noise from a handheld thermal imaging system via FPGA implementation will be mentioned. Additionally experimental results, regarding the image performance improvement and the source usage will be explained.
Proc. SPIE. 10223, Real-Time Image and Video Processing 2017
KEYWORDS: Field programmable gate arrays, Video acceleration, Video, Video compression, Video processing, Video coding, Imaging systems, Digital signal processing, Defense technologies, Computer programming, Quantization
Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA’s lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.