In this work we assess the feasibility of ZnO films deposited from a sol gel precursor as a material for thin film charged particle detectors. There are many reports of polycrystalline ZnO thin film transistors (TFTs) in the literature, deposited by sputtering, pulsed laser deposition, and sol gel. There are also reports of sol gel derived ZnO doped with Li or Mg to increase the resistivity, however, these works only measure resistivity of the films, without determining the effect of doping on the carrier concentration. We study the effects of doping the ZnO with Mg and Li as well as the effects of thickness on the films’ resistivity, mobility, and carrier concentration, since these material parameters are critical for a charged particle sensor. Carrier concentration is particularly important because it must be kept low in order for the intrinsic region of a p-i-n diode to be depleted. In order to accomplish this we fabricate and electrically characterize test structures for resistivity, test structures for hall measurement, common back-gate TFTs, and metal-insulator-semiconductor (MIS) capacitors. We also conduct physical characterization techniques such as x-ray diffraction (XRD), atomic force microscopy (AFM), electron microscopy, UV-Vis spectroscopy, and ellipsometry to determine the effect of doping and film thickness on the microstructure and optical properties of the ZnO.
In this work we demonstrate high performance and low-power n-type inverters using solution-based CdS as the semiconductor in thin film transistors. Our fabrication process consists of five mask levels and a maximum temperature of 150 °C. The CdS is deposited using chemical bath deposition at 70 °C to provide full compatibility with flexible substrates. Isolated TFTs showed mobilities up to 10 cm<sup>2</sup>/V-s and threshold voltages of approximately 0.5V. Inverters were biased at 1, 3 and 5 V, resulting in maximum gains in the range of 60 at V<sub>DD</sub> = 3V. The devices and circuits are fully patterned using standard photolithographic techniques that can be used to design more complex circuitry for flexible and large area electronic applications. In addition we used an extraction parameter method for our TFTs that allows the use of regular SPICE simulation software to design and test the circuits. Our simulations are in good agreement with the experimental data for isolated devices and inverters. Other circuits such as NAND gates are also demonstrated.