The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device
technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second
generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical
part of technology enablement as scaling has become more challenging and the industry pushes the limits
of EUV lithography. The working partnership between the design teams and the process development
teams typically involves an iterative approach to evaluate the manufacturability of proposed designs,
subsequent modifications to those designs and finally a design manual for the technology. While this
approach has served the industry well for many generations, the challenges at the Beyond 7nm node require
a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout
optimization where we remove the iterative component of DTCO and replace it with an optimization that
achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects.
Solved together, this “design intent” approach can more quickly achieve superior lithographic results while
still meeting the original device’s functional specifications.
Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using
design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either
supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic
behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall
optimization. We will show the benefit of the “design intent approach” on both bidirectional and
unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO
approach. Thus demonstrating the benefit of allowing the design to float within the specified range.
Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on
some minimal set of functional requirements and process constraints.
The objective of this work is to describe the advances in the use of C-Quad polarized illumination
for densest pitches in back end of line thin wire in 32m technology and outlook for 28 nm
technology with NA of 1.35 on a 193nm wavelength scanner. Through simulation and experiments,
we found that moving from Annular to C-Quad illumination provides improvement in intensity and
contrast. We studied the patterning performance of C-Quad illumination for 1D dense, semi dense,
isolated features with and without polarization. Polarization shows great improvement in contrast
and line edge roughness for dense pattern. Patterning performance of isolated and semi-isolated
features was the same with and without polarization.
For 32 nm test chips, aggressive resolution enhancement technology (RET) was required for 1x metal layers to enable
printing minimum pitches before availability of the final 32 nm exposure tool. Using a currently installed immersion
scanner with 1.2 numerical aperture (NA) for early 32 nm test chips, one of the RET strategies capable of resolving the
minimum pitch with acceptable process latitude was dipole illumination. To avoid restricting the use of minimum pitch
to a single orientation, we developed a double-expose/single-develop process using horizontal and vertical dipole
illumination. To enable this RET, we developed algorithms to decompose general layouts, including random logic,
interconnect test patterns, and SRAM designs, into two mask layers: a first exposure (E1) of predominantly vertical
features, to be patterned with horizontal dipole illumination; and, a second exposure (E2) of predominantly horizontal
features, to be patterned with vertical dipole illumination. We wrote this algorithm into our OPC program, which then
applies sub-resolution assist features (SRAFs) separately to the E1 and E2 masks, coordinating the two to avoid
problems with overlapping exposures. This was followed by two-mask OPC, using E1 and E2 as mask layers and the
original layout (single layer) as the target layer. In this paper, we describe some of the issues with decomposing layout
by orientation, issues that arise in SRAF application and OPC, and some approaches we examined to address these
Implementations of scatterometry in the back end of the line (BEOL) of the devices requires design of advanced
measurement targets with attention to CMP ground rule constraints as well as model simplicity details. In this paper
we outline basic design rules for scatterometry back end targets by stacking and staggering measurement pads to
reduce metal pattern density in the horizontal plane of the device and to avoid progressive dishing problems along
the vertical direction. Furthermore, important characteristics of the copper shapes in terms of their opaqueness and
uniformity are discussed. It is shown that the M1 copper thicknesses larger than 100 nm are more than sufficient for
accurate back end scatterometry implementations eliminating the need for modeling of contributions from the buried
layers. AFM and ellipsometry line scans also show that the copper pads are sufficiently uniform with a sweet spot
area of around 20 μm. Hence, accurate scatterometry can be done with negligible edge and/or dishing contributions
if the measurement spot is placed any where within the sweet spot area. Reference metrology utilizing CD-SEM and
CD-AFM techniques prove accuracy of the optical solutions for the develop inspect and final inspect grating
structures. The total measurement uncertainty (TMU) values for the process of record line width are of the order of
0.77 nm and 0.35 nm at the develop inspect and final inspect levels, respectively.
193nm immersion lithography might have to incorporate a top layer coat to prevent leaching and contamination. Additionally, immersion and future lithography will require lowering the photoresist thickness. It has been reported in literature that the diffusion coefficient of small acid molecules reduces as the resist thickness is reduced below 200 nm. The goal of this paper is to understand how, the use of a top coat, changing resist thickness and changing the substrate affect line edge roughness (LER). The study is conducted using dry 193 nm lithography. It was found that the use of a top coat helps to improve LER for 193 nm dry resist process. Improvement in LER with the use of top coat can be explained by a change in intrinsic bias of the resist. LER was also studied as a function of resist thickness, by changing resist thickness from 790 Å to 2200 Å. It was found that LER is a strong function of resist thickness. At thickness less than about 1300 Å, LER increases, with a more pronounced effect as resist thickness is decreased further. LER was also studied as a function of substrate. Two substrates, organic bottom anti-reflection coating (BARC) and an inorganic silicon oxynitride film (SiON), were used in the present study. For ultra-thin resist films, less than 1300 Å thick, it was found that the SiON substrate produced greater LER compared with the organic BARC substrate. The data compiled provides a fundamental understanding of LER behavior and will eventually help in better control of LER for future generation devices.
Patterning of dense gratings with sub-wavelength pitches presents a challenge that can be addressed using Resolution Enhancement Techniques (RETs) such as dipole illumination, with the dipole axis perpendicular to the dense line orientation. However, this approach leads to pitch and orientation limitations that must be accommodated in layout practices and design rules. In this work we evaluate the impact that dipole illumination has on the process window of isolated lines and loose pitch lines parallel and orthogonal to the dipole axis, and demonstrate the use of OPC and design restrictions to minimize this impact. Semi-dense and isolated features need to be treated as a function of their orientation with respect to the dipole. Specifically, isolated features oriented along the axis of the dipole have larger process margins than the same feature oriented perpendicular to this axis. We systematically explore the process margins for various CDs, pitches and orientations, and compare the results with simulations. We demonstrate that the dipole illumination restricts the ranges of sizes, pitches and orientations that can be printed with sufficient process margin. Knowledge of these restrictions and comparing them with simulation enables us to evaluate the suitability of simulations as a predictor for design rules to restrict layout. The results enable us to propose design rules that would enable single-mask solutions for layers using dipole illumination.