Ultrathin (1–10 nm) Cu and Au films were prepared on the silicon and quartz substrates by magnetron sputtering at room temperature. We measured the transmission coefficient of the films at a wavelength of 3cm and analyzed a surface morphology of these films. It was shown that the films with thicknesses less than 7.5 nm (Au) and 3 nm (Cu) are almost transparent for microwaves. This effect is explained by quick oxidation of Cu and the complex surface morphology of nanometer thick films. The Au film morphology is evolved with increasing average Au thickness d from hemispherical islands initially (1.0 nm<d<5.0 nm) to partially coalesced worm-like island structures (d=10 nm).
A study of copper (Cu) diffusion into silicon substrates through TaNx and Ta/graded Ta(N)/TaN multilayer diffusion barriers was investigated based on an experimental approach. TaNx and Ta/graded Ta(N)/TaN thin films were deposited by magnetron sputtering under argon (Ar) and Ar-nitrogen (N) plasma. The influence of the N2 partial pressure on the microstructure and the electrical properties is reported. The efficiency of TaNx layers and Ta/graded Ta(N)/TaN multilayer diffusion barriers was investigated after annealing at temperatures between 300 and 600◦C in Ar.
It is well known that due to interaction between Cu and Si in the regions of source and drain copper interconnections should not be in direct contact with Si. In this study the barrier properties of Hf-based thin films were investigated. Hafnium nitride films (15nm) and multilayer Hf-Si structures (50 alternate 0,2 nm-Hf and 0,4 nm-Si layers) were prepared by electron beam evaporation. Hf-Si sandwiches were annealed at 700°C and 900°C for 2 min to form silicide.
Then 100 nm thick copper layers were deposited on the samples. For the Cu/HfNx/Si contact system the interfacial reactions between Cu, Hf and Si were observed after annealing at 500°C for 30 min by profile Auger analysis. The HfNx barrier fails and Cu atoms penetrate into the Si substrate. On the other hand Auger analysis results for Cu/HfSix/Si structure showed that there were not diffusion of Cu atoms in barrier layer and Si substrate. Findings demonstrate that hafnium silicide barrier layers can be used to prevent interfacial reactions between copper interconnections and silicon regions of source and drain.
In this work we present the results of simulation of vertical MOS transistor with electrically variable shallow junctions in
ISE TCAD. Transistor with fully silicided gate electrodes, two heavy doped delta-layers in the channel region and ZrO2
as a gate dielectric has been simulated. The simulation used different carrier transport and mobility models. High values
of on-state current have been obtained during the simulation process (~1.2 mA/μm). Different voltage regimes for middle
and side gates have been assumed. Values of direct leakage current from drain to source got from simulation are
relatively low and amount to approximately 0.02 μA/μm2. These values show that use of electrically variable junctions
and doped delta-layers really suppresses short-channel effects and reduces direct leakage current from drain to source.
Technology of electrically variable junctions allows to employ vertical transistor into high-performance logic
Zirconium oxide (ZrO2) films have been deposited on cleaned and heated p-type Si (100) substrates by electron-beam
evaporation technique. It is shown that the intermediate SiO2 layer on ZrO2/Si interface is absence. The W/YSZ/Si and
Mo/YSZ/Si structures with 3÷20-nm-thick dielectric layers were formed by electron-beam evaporation technique. The
fixed charge densities in 3-nm-thick YSZ layers are 3x1010 - 3.7x1010cm2, leakage current density at a voltage -1V