In order to cater the needs of the users in the communication field in terms of high speed, high bandwidth, error free reception, researchers focused their attention towards BISDN/ATM in the recent years. Since the major efficiency of the ATM networks depends on the ATM switching, in this paper, we focused our attention towards high throughput of an ATM switch architecture. The Banyan switch architecture is taken for our study in this paper. We have simulated an 8 X 8 Banyan architecture with the proposed scheme of using RS coder and decoder. The Banyan architecture has been studied for its performance with Self-Similar traffic. The performance of the proposed architecture in terms of cell loss and average delay versus the cell arrival rate is presented.