In order to continue scaling down the feature sizes of the devices, EUV lithography is regarded as the most
powerful candidate for patterning. So It has being studied to overcome the several issues such as source
power for high throughput to apply volume production, mask defectivity from mask blank, RLS (Resolution,
LWR & Sensitivity) trade off, which is the intrinsic property of EUV resist, and so on.
For 2x nm node DRAM, dense contact hole, which has 3x nm half pitch (hp), has been issued to be made so
far. There are two well-known methods for pattering; hole double patterning with ArF immersion lithography
and single patterning with EUV lithography. EUV is more simple solution than hole double patterning for
3xnm hp dense contact hole, if it has large process window and comparable CD uniformity. Fortunately,
EUV process already has larger process window than that of ArF immersion because its k1 value is a little bit
high. But CD (critical dimension) uniformity and pattern profile were very poor in our initial result.
Therefore it needs a lot of efforts to improve and compete against double patterning.
The double patterning performance for 3xnm hp contact hole has been shown last year. In this paper, we
will investigate on improving CD uniformity and pattern profile for 3x nm hp contact hole with several
methods. Finally, the performance of EUV, which is achieved by our experiments, is being compared with
that of double patterning in terms of CD uniformity and pattern profile.
In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches
to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning
technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both
stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In
terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal
lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process
stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x
nm hole patterning process using double patterning technology combined with negative tone development (NTD).
Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD
with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be
discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through
NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be
As EUV lithography nears pilot-line stage, photolithography modeling becomes increasingly important in order for
engineers to build viable, production-worthy processes. In this paper, we present a comprehensive, calibrated
lithography model that includes optical effects such as mask shadowing and flare, combined with a stochastic resist
model that can predict effects such as line-edge roughness. The model was calibrated to CD versus pitch data with
varying levels of flare, as well as dense lines with varying degrees of mask shadowing. We then use this model to
investigate several issues critical to EUV. First, we investigate EUV photoresist technology: the impact of
photoelectron-PAG exposure kinetics on photospeed, and then we examine the trade-off between LWR and photospeed
by changing quencher loading in the photoresist model. Second, we compare the predicted process windows for dense
lines as flare and lens aberrations are reduced from the levels in the current alpha tools to the levels expected in the beta
tools. The observed interactions between optical improvements and resist LWR indicate that a comprehensive model is
required to provide a realistic evaluation of a lithography process.
Contact hole patterning is more difficult than line/space patterning as mask error factor is higher in contact hole
patterning which has 2-dimensional patterns. As the industry moves towards 40nm node and beyond, the challenges
associated with contact hole having a manufacturable process window have become increasingly difficult. Current
1.35NA ArF lithography is capable of printing 50nm contact hole with a stable process window at best. Conventional
contact hole patterning processes such as resist reflow and RELACS are no longer able to be used for half-pitch 40nm
contact hole pattern because we have to shrink not only hole diameter but also pattern pitch. In this paper, we will
demonstrate and compare the patterning performance of the mesh patterning processes including litho-etch-litho-etch, cap freezing and self freezing process.
In this paper, we will present experimental results on sub-40nm node patterning of DRAM and some technical issues for capping freezing in simplified double patterning lithography. Lithography resolution limit of single pattern is 40nm in ArF immersion process. For sub-40nm patterning, we have to use double patterning lithography or EUV process. But, double patterning lithography process is very complicated and expensive solution. And EUV volume production technology will be not ready until 2012. Therefore, we have tried a simplified double patterning lithography.