Photolithography for the formerly "non-critical" implant blocking layers is becoming more challenging as edge
placement control budgets for junction definition shrink with each node. In addition to the traditional proximity
effects associated with the implant layer mask, the underlying active and gate layers can interact through a variety of
mechanisms to influence the edge placement of the developed implant layer. These mechanisms include bulk
reflectivity differences, resist thickness thin film interference effects, reflective notching from pattern sidewalls,
reflections from curved surfaces, focus differences, and more. While the use of organic developable bottom
antireflection coating (dBARC) can be effective in minimizing these influences, it does represent an added
complexity and cost, and processes are still relatively immature. Without such a dBARC, the CD variation due to
underlying layers can easily exceed 50 nm, or more than 25% of the target dimension. We propose here a
framework for modeling and correcting for these underlayer effects. The approach is based upon calibration of an
optical model representing only implant mask proximity effects and two additional optical models which represent
the effects of the underlayer topography. Such an approach can be effective in delivering much improved CD
control for complex layouts, and represents only a small impact to full-chip correction runtime.
Implant layer patterning is becoming challenging with node shrink due to decreasing critical dimension (CD) and usage
of non-uniform reflective substrates without bottom anti-reflection coating (BARC).
Conventional OPC models are calibrated on a uniform silicon substrate and the model does not consider any wafer
topography proximity effects from sub-layers. So the existing planar OPC model cannot predict the sub-layer effects
such as reflection and scattering of light from substrate and non-uniform interfaces. This is insufficient for layers without
BARC, e.g., implant layer, as technology node shrinks.
For 45-nm and larger nodes, the wafer topography proximity effects in implant layer have been ignored or compensated
using rule based OPC. When the node reached 40 nm and below, the sub-layer effects cause undesired CD variation and
resist profile change. Hence, it is necessary to model the wafer topography proximity effects accurately and compensate
them by model based OPC. Rigorous models can calculate the wafer topography proximity effects quite accurately if
well calibrated. However, the run time for model calibration and OPC compensation are long by rigorous models and
they are not suitable for full chip applications. In this paper, we demonstrate an accurate and rapid method that considers
wafer topography proximity effects using a kernel based model. We also demonstrate application of this model for full
chip OPC on implant layers.
Optical Proximity Correction (OPC) Model Calibration has required an increasing number of measurements as the
critical dimension tolerances have gotten smaller. Measurement of two dimensional features have been increasing at a
faster rate than features with one dimensional character as the technologies require better accuracy in the OPC models
for line-end pull-back and corner rounding. New techniques are becoming available from metrology tool manufacturers
to produce GDSII contours of shapes from wafers and modeling software has been improved to use these contours.
The challenges of implementing contour generation from the SEM tools will be discussed including calibration methods,
physical dimensions, algorithm derivations, and contour registration, resolution, scan direction, and parameter space