Electrical validation of through process optical proximity correction verification limits in 32-nm process technology is presented. Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence of each process conditions. The design of electrical layouts is extended to subdesign rules to force failure and derive better correlation between electrical and simulated outputs. Some of these subdesign rule designs amplify the failures induced by an exposure tool, such as optical aberrations. Observations in this regard are reported. Sensitivity with respect to dimensions, orientations, and wafer distribution are discussed in detail.
Electrical validation of through process OPC verification limits in 32nm process technology is presented in this paper.
Correlation plots comparing electrical and optical simulations are generated by weighting the probability of occurrence
of each process conditions. The design of electrical layouts is extended to sub ground rules to force failure and derive
better correlation between electrical and simulated outputs. Some of these sub ground rule designs amplify the failures
induced by exposure tool, such as optical aberrations. Observations in this regard will be reported in the paper.
Sensitivity with respect to dimensions, orientations and wafer distribution will be discussed in detail.
Electrically testable structures (such as serpentines for testing opens and serpentine/combs for testing shorts) with
varying post-OPC dimensions have been incorporated into test reticles, which were then used to process wafers through
electrical test. Process window OPC verification was run on the same structures, thus allowing correlation of electrical
yield to OPC-verification results. By combining OPC verification results with probability of occurrence for the various
process conditions used in OPC verification, a predicted yield can be calculated. Comparisons of electrical yield to
predicted yield are used to demonstrate a methodology for verifying (or setting) failure limits. Although, in general, the
correlation between electrical and predicted yield is reasonable, various issues have been identified which impact this
correlation, and make the task of accurately predicting yield difficult. These issues are discussed in detail in this paper.
Complex Optical Proximity Correction (OPC) must be deployed to meet advanced lithography requirements. The OPC
models are used to convert input design shapes into mask data that often deviate significantly from both the initial design
and the final wafer image in resist. The process includes selective shape biasing, applying pattern-specific corrections,
and, possibly, modeling the effect at multiple exposure conditions. It is important to verify the results of the OPC model
and this is done by invoking OPC verification programs. The verification models identify points of failure to specific
criteria. Failure can be defined as the simulated resist dimension below which a feature will not survive additional
processing. Since these models are built for use in OPC verification, they may only be well-calibrated at feature sizes
near target. This can introduce uncertainties in the failure predictions. This paper will explore options for validating the
OPC verification models and methods. While wafer prints are an obvious source of feedback on the simulated results,
there are also options at mask level. In this paper, we study the effect of programmed defects at wafer level, mask level
and through OPC verification method. For each test case, five points in the process window space are chosen to provide
comparison data between OPC verification measurements, mask-level intensity contour measurements - e.g. Aerial
Image Microscope System (AIMS), and wafer measurement of patterned photoresist. The results permit correlation to
measurable metrics and provide an improved understanding of OPC verification validity.
One of the challenges associated with shrinking design dimensions is finding photomask inspection settings which
achieve sufficient defect detection capabilities while supporting aggressive Optical Proximity Correction (OPC). The
most recent technology nodes require very aggressive and advanced Resolution Enhancement Techniques (RETs) which
involve printing small features that are challenging for mask inspection tools. We examine the problems associated with
constraining Models-Based OPC with mask inspection driven rules. We give examples of a 45nm technology node
contact layer design which will receive sub-optimal OPC treatment due to mask inspection constraints. We then take the
mask defect specification typically used for this mask layer, and use Monte Carlo simulation methods to place minimum
sized simulated defects in various locations in close proximity to these sensitive layouts. Simulations of the optimal OPC
are compared to optimal OPC with defects, and to the sub-optimal constrained OPC. Using knowledge about the
frequency of small defects on masks, one can compare the risks associated with small mask defects to the risks
associated with sub-optimal OPC. This exercise demonstrates that there are some instances where mask rules based on
inspection capabilities and defect sensitivity alone can be problematic, and that OPC requirements need to be taken into
account when choosing a defect specification and an inspection strategy. We conclude by proposing a strategy for
balancing these requirements in a practical manner.
In this paper we report on alternate solutions to protect against process variability - while also focusing on minimizing
simulation time. We have investigated a variety of techniques, including the use of aerial image parameters to flag sites
that might be sensitive to changes in dose, a mask error enhancement factor (MEEF) check based on biasing of the
optical proximity correction (OPC) layer to reflect mask variations, and a sorting approach where sites with suspect
parameters (e.g. high MEEF or poor aerial image quality, such as low slope) are simulated using multiple process
conditions. All of these techniques represent shortcuts as compared to simulations of the full chip at multiple process
conditions, and thus savings in CPU time. However, use of these short cuts can have several down-sides: first, increased
risk of missing a real error, and second, increases in the number of false errors reported (where false errors are sites
which are predicted to fail, but actually have an adequate window to allow for process variability). The challenge is to
find methods to make the short cuts as selective as possible, so that they will flag all potentially failing sites, without
flagging too many false errors.
At the 65 nm node and beyond, printing the dense and isolated pitches as well as the 2D patterns within tight tolerance across the full range of known process conditions becomes a major challenge, and even more critical in the context of double exposure masks. Post-OPC simulation at nominal conditions is not sufficient to accurately assess and disposition severe errors and monitor residual proximity effects and their implications such as channel length variation.
In this paper, we explore a methodology that adopts multiple simulations to model the variability in the lithography process. This approach is predicting the process behavior by the modulation of the related lithography parameters, such as: dose, focus, and overlay. The goal is to identify the unacceptable deviation of the printed image from the designed target due to process variations. The method also provides a better statistical evaluation of the quality and robustness of the implemented Resolution Enhancement Techniques (RET) & Design for Manufacturability (DfM) solution.
In this paper we will describe the implementation of a system for model-based verification of post OPC data into a manufacturing data flow. Verification is run automatically, upon OPC completion, on the critical levels for every chip run in the 130nm node and beyond to ensure that OPC errors are caught before hardware is committed in the manufacturing line. The checks are derived from the design rule manual, and are written to cover the intent of the design rules. Some of the challenges of implementing a robust model-based verification solution for manufacturing will be discussed, including resource requirements, data management, cycle time, and the creation of a closed loop system to ensure that verification is completed on all chips. The benefits of implementing model-based verification include improved feedback to lithography and OPC teams, enabling constant improvement, as well as increasing the probability of first time right manufacturing of a new chip design.
This paper investigates the implementation of sub-resolution assist features (SRAFs) in high performance logic designs for the poly-gate conductor level. We will discuss the concepts used for SRAF rule generation, SRAF data preparation and what we term "binary" optical proximity correction (OPC) to prevent catastrophic line-width problems. Lithographic process window (PW) data obtained with SRAFs will be compared to PW data obtained without SRAF. SRAM cells are shown printed with annular illumination and SRAFs, for both the 130 nm and 100 nm logic nodes as defined by the International Technology Roadmap for Semiconductors (ITRS). This study includes a comparison of the experimental results of SRAMs printed from designs corrected with rule-based OPC to those printed from designs corrected with model-based OPC.
This paper investigates the design of targets for in-line lithography process control. The need for wafer-level understanding and control of defocus has driven the development of several of methods for detecting focus shifts. The methods are typically based on measurements of line-end shortening and use optical methods. This work starts a dual-tone pair of arrays, one built from resist lines and the other from resist troughs. These process control targets area also known as schnitzls. The influence of the shape of the individual lines, the line pitch and separation of arrays are investigated using both simulations and wafer resist CDSEM measurements. A theoretical model was applied to all data to enable objective comparison of different designs. A guide to dose and defocus target design for process window monitoring is provided as part of the summary.
Sub-resolution assist features (SRAF) have been shown to provide significant process window enhancement and across chip line-width variation reduction when used in conjunction with modified illumination lithography. Work previously presented at this conference has focused on the optimization of sraf design rules that specify the predominantly one dimensional placement and width of assist features as a function of layout pitch. This paper will recount the optimization of SRAF style options that specify how SRAF are to behave in realistic two dimensional circuit layouts. Based on the work done to strike the correct balance between sraf manufacturability, CAD turnaround time, and lithographic benefit in IBM's early product implementation exercises, the evolution of sraf style options is presented. Using simulation as well as exposure data, this paper explores the effect of various two dimensional sraf layout solutions and demonstrates the use of model based verification in the optimization of sraf style options.
Scanned probe microscopy (SPM) and optical thickness measurements were used to study conformality of a 0.5 micrometer-thick photoresist and two different ARCs (75 nm thick). One ARC (ARC A) was a thermally stable system as applied. (The molecular weight did not change with the normal post-apply bake.) The other ARC (ARC B) was a thermally cross- linking system. (Cross-linking occurs on the wafer during post-apply bake, thus increasing molecular weight.) Three different step heights, ranging from 44 to 150 nm, were studied. Two measures of conformality were used: the 'planarization length' or distance from an edge for which the material reaches nominal thickness, and the film thickness loss over a given feature width. For the photoresist, the planarization length was 30 - 50 micrometer, and a 1 micrometer-wide ridge was almost completely planarized. (Resist thickness loss was 70 - 80% of the step height, vs 100% for complete planarization.) As expected, the much thinner ARC films were more conformal than the resist film; however, each behaved quite differently: the thermally stable system (ARC A) was more conformal than the thermally cross- linking system (ARC B). The planarization length for ARC A was 5 - 10 micrometer while, for ARC B, it was 20 - 40 micrometer. ARC A also showed less thickness loss for 1 to 10 micrometer- wide ridges. For a 1 micrometer-wide ridge, ARC A showed a thickness loss of 40% of the step height; for ARC B, the loss was 50%. For a 10 micrometer-wide ridge, the thickness losses were 5% and 15% for ARCs A and B, respectively.
The relative benefit of using a broadband illumination system to reduce thin-film interference is impacted when using thinner resist films. For example, with a 1 micrometer resist film, a 43% reduction in swing curve is predicted for broadband vs. monochromatic illumination, while for a 0.5 micrometer film the reduction is only 25%. For a 0.5 micrometer resist film over an organic ARC exposed on a broadband system, such as a SVGL Micrascan-2, both simulations and experimental data show a 10 - 16% swing curve. These are results for an ARC with a relatively low absorbance (k equals .22). Results are given for several approaches that were investigated to reduce this swing curve, including improved ARC materials and resist thickness optimization; e.g., with a CVD ARC, the swing curve can be reduced to less than 10 nm. Resist and ARC thickness optimizations are normally done independently; however, resist and ARC thicknesses may not be independent. Much of the thickness variation is caused by the topography, with the resist and ARC behaving in the same qualitative fashion (e.g., both the ARC and resist tend to planarize over a ridge; thus, both will be thinner over a ridge). A method for optimizing interdependent resist and ARC thicknesses is also presented; it couples modeled linewidth data with ARC and resist planarization data to predict the optimum resist and ARC thickness.
Thin-film interference effects change the fraction of energy available for absorption in the photoresist, resulting directly in linewidth changes. This paper addresses the absorbed energy variation due to the variation in films underlying the photoresist. An optical thin-film interference model is developed and compared to measured reflectivity data for continuously varying silicon nitride under DUV positive photoresist. The model is used to predict an improved linewidth control of greater than a factor of three for broadband over monochromatic illumination, which is also experimentally verified. In addition, simulated and measured data are presented with and without an antireflective coating underlying the resist.