Memristors were vertically integrated with CMOS circuits using nanoimprint lithography (NIL), making a transistor/memeristor hybrid circuit. Several planarization technologies were developed for the CMOS substrates to meet the surface planarity requirement for NIL. Accordingly, different integration schemes were developed and optimized. UV-curable NIL (UV-NIL) using a double layer spin-on resists was carried out to pattern the electrodes for memristors. This is the first demonstration of NIL on active CMOS substrates that are fabricated in a CMOS fab. Our work demonstrates that NIL is compatible with commercial IC fabrication process. It was also demonstrated that the memristors are integratable with traditional CMOS to make hybrid circuits without changing the current infrastructure in IC industry.
Nanoimprinting lithography (NIL) is being evaluated as a possible method for meeting lithography requirements for
semiconductor imaging at 32nm half-pitch nodes and below. NIL is included in the <i>International Technology Roadmap
for Semiconductors </i>(ITRS) as a potential choice for advanced lithography. In this technology, the template, or mold, is a
critical component in achieving the requirements for feature size and defectivity. Since NIL is a contact imaging
technique, one of the issues is the high probability of defects while imprinting. Since the template is in contact with a
fluid during the imaging process, maintaining the required template cleanliness needed to met the ITRS requirements
without damaging or changing critical dimensions is an important process. In this paper we discuss the results obtained
from several different NIL template cleaning methods using SEMATECH's Mask Blank Development Center facilities.
The effectiveness of different operating conditions as well as several different chemistries is compared.
Increasing numbers of MEMS, photonic, and integrated circuit manufacturers are investigating the use of Nano-imprint Lithography or Step and Flash Imprint Lithography (SFIL) as a lithography choice for making various devices and products. Their main interests in using these technologies are the lack of aberrations inherent in traditional optical reduction lithography, and the relative low cost of imprint tools. Since imprint templates are at 1X scale, the small sizes of these structures have necessitated the use of high-resolution 50KeV, and 100KeV e-beam lithography tools to build these templates. For MEMS and photonic applications, the structures desired are often circles, arches, and other non-orthogonal shapes.
It has long been known that both 50keV, and especially 100keV e-beam lithography tools are extremely accurate, and can produce very high resolution structures, but the trade off is long write times. The main drivers in write time are shot count and stage travel. This work will show how circles and other non-orthogonal shapes can be produced with a 50KeV Variable Shaped Beam (VSB) e-beam lithography system using unique pattern transforms and primitive shapes, while keeping the shot count and write times under control. The quality of shapes replicated into the resist on wafer using an SFIL tool will also be presented.
Nanoimprint lithography is a contact-lithography technology invented in 1996 as a low-cost alternative to photolithography for researchers who need high resolution patterning. Initially perceived as a trailing-edge technology for low-cost device fabrication, it has been recently demonstrated to achieve sub-10 nm resolution and alignment, which equal or surpass even the most advanced photolithography today. At Hewlett-Packard, we have successfully used it to fabricate switchable molecular memory arrays with a dimension of 65 nm half pitch. Nanoimprint has been placed on the International Technology Roadmap for Semiconductors (ITRS) as a candidate for next-generation lithography (NGL) for insertion in the 32 nm node in Y2013. The switch from using light to using contact to pattern will indeed bring new challenges, the most important of which are alignment and the 1x mask/template. For alignment, one imprint tool maker has achieved alignment of +/-7 nm 3 sigma using Moire patterns. For template fabrication, the lack of OPC and other sub-resolution features produced large savings in patterning, but it is nearly cancelled out by the need for more aggressive inspection because of the smaller tolerable defect size. The two combined to make the predicted cost of nanoimprint template to be similar to photomasks for 45-nm half pitch. At 32-nm half pitch, EUVL masks do not have complicated sub-resolution features and are predicted to be cheaper than comparable nanoimprint templates provided that the former’s defect levels can be reduced to what is required for economical manufacturing. In both cases, the challenges are not insurmountable and solutions are being actively pursued. However, if nanoimprint is indeed the disruptive technology to photolithography, it needs to take its initial aim at the low-end market rather than mount a frontal challenge at semiconductor manufacturing, which is the high-margin customers that photolithography will pursue and protect at all cost. The recent development in nanotechnology will lead to the commercialization of a new class of nanoscale devices requiring a high-resolution lithographic technique that does not have all the functionalities of photolithography. This approach will provide an initial customer base for nanoimprint to develop and improve and position it to challenge photolithography in the distant future.