The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (packing density) a scanner is also expected to provide tight control of the Across Chip Linewidth Variation, ACLV, (transistor speed). An important component of ACLV is lens aberrations. Techniques that measure in-situ the lens aberrations are now available. In a previous paper we reported good agreement between the first 25 Zernike coefficients measured in-situ using one of these techniques ARTEMIS and PMI (Phase Metrology Interferometry) data collected at the lens manufacturer. However questions have arisen as to the practicality of ARTEMIS, especially in view of its heavy reliance on a very large number of SEM images. We have measured the first 25 Zernike coefficients for 13 ASML 500/700 DUV Step & Scan systems in a high-volume wafer fab. In this paper we report on certain enhancements that were made to the best practice of ARTEMIS. We will also present a summary of the measurements taken and our first attempt to cluster the tools according to the aberrations measured.
Aberrations, aberrations, here there everywhere but how do we collect useful data that can be incorporated into our simulators? Over the past year there have no less than 18 papers published in the literature discussing how to measure aberrations to answering the question if Zernikes are really enough. The ability to accurately measure a Zernike coefficient in a timely cost effective manner can be priceless to device manufacturers. Exposure tool and lens manufacturers are reluctant to provide this information for a host of reasons, however, device manufacturers can use this data to better utilize each tool depending on the level and the type of semiconductors they produce. Dirksen et al. first discussed the ring test as an effective method of determining lens aberrations in a step and repeat system, later in a scanning system. The method is based on two elements; the linear response to the ring test to aberrations and the use of multiple imaging conditions. The authors have been working to further enhance the capability on the test on the first small field 157 nm exposure system at International SEMATECH. This data was generated and analyzed through previously discussed methods for Z5 through Z25 and correlated back to PMI data. Since no 157nm interferemetric systems exist the lens system PMI data was collected at 248nm. Correlation studies have isolated the possible existence of birefringence in the lens systems via the 3-foil aberration which was not seen at 248nm. Imaging experiments have been conducted for various geometry's and structures for critical dimensions ranging from 0.13micrometers down to 0.10micrometers with binary and 0.07micrometers with alternating phase shift mask. The authors will review the results of these experiments and the correlation to imaging data and PMI data.
The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (improving packing density), a scanner is expected to provide tight linewidth control across the chip, ACLV (transistor speed). An important component of ACLV is lens aberrations. Recently techniques that allow the measurement in-situ of aberrations using Zernike coefficients have become available. We have measured the first 25 Zernike coefficients in two ASML PAS 500/700D DUV Step & Scan systems. The measured Zernikes are in agreement with PMI (Phase Measurement Interferometry) data collected at the lens manufacturer within 3.8 nm or less. We find good agreement between the variation of the Z<SUB>5</SUB> (first order astigmatism) coefficient and the optimum focus offset between horizontal and vertical lines measured using FOCAL. There is also good agreement between Z<SUB>5</SUB> and the linewidth difference between 160 nm horizontal and vertical lines with a 330 nm pitch. The lines were printed using an NA equals 0.68, (sigma) equals 0.70 on 3,800 angstrom of resist on top of an inorganic BARC. We find good correlation between the Z<SUB>7</SUB> coefficient (first order coma) and linewidth variation across the slit. We also found that the effect of the aberrations as measured by linewidth range is a function of pitch. Linewidth range decreases as the duty ratio increases, reaching a minimum at a duty ratio of 1:1.44, and then increases again as the lines become isolated. This is surprising because these intermediate pitches also have the smallest focus-exposure window. We conclude that knowing the Zernike coefficients provides us with a very powerful tool to characterize our exposure tools. However to fully realize the benefit of this new tool we must improve the accuracy of our simulation tools.
Step and Scan technology has matured for the current generation of semiconductor lithography tools and has become the standard for most new fabs and fab expansions. It is estimated that for the year 1999, more than 64 percent of new exposure tool shipments from all vendors were step and scan platforms. For economical mass production in sub 180 nm applications, DUV and i-line lithography have to be combined with critical layers that are exposure during DUV. Semi- critical and non-critical layers are exposed using i-line. The choice to use a stepper ora scanner for the i-line platform becomes critical in terms of operating cost and technical capability. This paper reports on the performance of high resolution, high throughput i-line scanners that are used in mix and match with DUV scanners. Advanced imaging capability is demonstrated on the ASML PAS 5500/400 i-line scanner as well as alignment performance on the most difficult layers using the ATHENA advanced alignment system. Matching strategies are presented along with a cost analysis showing the merits of using i-line scanners for semi- critical and non-critical layers in mix and match.
There is growing consensus that 350 nm design rules will be accomplished using i-line lithography. Recent developments in i-line lithography have pushed NA and field size to acceptable levels for 64 MB DRAM manufacturing. Simpler PSM technologies may be used to augment performance in first generation 64 MB DRAM manufacturing. Depending on the topography requirements, it may be necessary to have more process latitude at critical line/space layers. I-line lithography, with conventional binary intensity masks (BIM) should provide adequate process latitude at 400 nm design rules. Incremental improvements in process latitude at feature sizes around this design rule can be obtained using attenuated phase PSM technology. This paper presents data on the implementation of BIM and various PSM technologies in conjunction with a variable NA, variable (sigma) i-line stepper. Optimization of NA and (sigma) have been performed using the various mask technologies to maximize process latitude at features sizes from 450 nm down to below 300 nm. Ultimately, a path is provided to achieve adequate lithographic performance for both first and second generation 64 MB DRAM manufacturing.
I-line lithography, together with single-layer resist processes, practically, have been limited to 0.45 micrometers design rules in the semiconductor industry. For design rules of 0.4 micrometers and below, several contrast enhanced methods have been proposed for i-line lithography, mainly phase shift masks, modified illumination methods, and surface imaging techniques, etc. This paper describes the sub-half micron process performance of 0.48 NA and 0.54 i-line steppers on various topography wafers which are suitable for 0.35 - 0.40 micrometers and 0.40 - 0.45 micrometers design rules. The latest high performance i-line resist and high contrast developing scheme have been chosen for this study. The process windows for the sub-half micron features on various topography wafers are reported. The feasibility to use these processes for the production with lower K<SUB>1</SUB> is also addressed.