High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers
allow the output frequency from a voltage controlled oscillator to be compared with a much lower external
reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers
are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper
we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three
dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative
and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency
synthesizer. The simulation results are in agreement with measured performance of the regenerative divider.
At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to
36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.