State of the art Extreme Ultra Violet Lithography (EUVL) gives high hope for further shrinkage of
semiconductor devices, but currently, EUVL is not ready for 2xnm node manufacturing and ArF immersion
must extend its capability in manufacturing 2xnm devices. Extending the limit of ArF requires varieties of
Resolution Enhancement Techniques (RET) such as inverse lithography (ILT) , double patterning (DPT),
spacer patterning and so on. One of the brightest candidate for extension of ArF for contact layer is negative
tone development (NTD), since this process utilizes the high contrast of the inverse tone of the mask for
patterning. NTD usually results in high process margin compared to conventional positive tone development
Therefore, in this paper we will study application of NTD from optical proximity correction (OPC)
and simulation perspective. We will first discuss difference of NTD from PTD. We will also discuss on how
to optimize NTD process in simulation perspective, from source optimization to simulation calibration. We
will also discuss what to look out for when converting PTD process to NTD process, including OPC models
to design rule modification. Finally, we will demonstrate the superiority of NTD process through modeling
and simulation results with considering these factors mentioned above.
In order to continue scaling down the feature sizes of the devices until extreme ultraviolet lithography (EUVL) reaches
to production capability, the alternative methods such as double patterning technology (DPT) and spacer patterning
technology (SPT) are applied for half pitch (hp) 2x~3x nm line / space imaging. In the storage node of DRAM, both
stable hole patterning and high dielectric constant (ε) material development are key factors to secure the capacitance. In
terms of hole patterning, we anticipate that hp 4x nm hole will be possible with combination of vertical and horizontal
lines. However, the patterning process for hp 3x nm hole has to find a solution in trade-off relationship between process
stability, complexity and cost of ownership (CoO) until EUVL is accomplished. In this paper, we will demonstrate 3x
nm hole patterning process using double patterning technology combined with negative tone development (NTD).
Contrary to general method (positive tone development with dark field mask) for hole patterning, intention to use NTD
with bright field mask will first be discussed. Evaluation and analysis of the simulated and experimental results will be
discussed for block CD uniformity improvement. In addition to patterning, overlay performance will be tested through
NXT 1950i to confirm DPT process feasibility. Finally, process integrations including etch process will be
As EUV lithography nears pilot-line stage, photolithography modeling becomes increasingly important in order for
engineers to build viable, production-worthy processes. In this paper, we present a comprehensive, calibrated
lithography model that includes optical effects such as mask shadowing and flare, combined with a stochastic resist
model that can predict effects such as line-edge roughness. The model was calibrated to CD versus pitch data with
varying levels of flare, as well as dense lines with varying degrees of mask shadowing. We then use this model to
investigate several issues critical to EUV. First, we investigate EUV photoresist technology: the impact of
photoelectron-PAG exposure kinetics on photospeed, and then we examine the trade-off between LWR and photospeed
by changing quencher loading in the photoresist model. Second, we compare the predicted process windows for dense
lines as flare and lens aberrations are reduced from the levels in the current alpha tools to the levels expected in the beta
tools. The observed interactions between optical improvements and resist LWR indicate that a comprehensive model is
required to provide a realistic evaluation of a lithography process.
As the DRAM node shrinks down to its natural limit, photo lithography is encountering many difficulties.
3Xnm DRAM node seems to be the limit for ArF Immersion. Until the arrival of EUV, double patterning (DPT) or
spacer double patterning (SPT) seems like the next solution. But the problem with DPT or SPT is that both increases
process step their by increasing the final costs of the device. So limiting the use of DPT or SPT is very important for
device fabrication. For 3Xnm DRAM, storage node is one of the candidates to eliminate DPT or SPT process. But this
method may cost lower process margin and degradation of pattern image. So, solution to these problems is very crucial.
In this study, we will realize storage node (SN) pattern for 3Xnm DRAM node with improved process margin. First we
will discuss selection of illumination for optimal condition second, correction of the mask will be introduced. We will
also talk about the usage of various RET such as model based assist feature. Value such as DOF, EL and CDU (critical
dimension uniformity) will be evaluated and analyzed.
In this paper, we will evaluate model assisted rule base SRAF. Model assisted rule base SRAF
combines the advantage of both model based SRAF and rule base SRAF to ensure high process margin
without the mask making difficulty with stable wafer output. Model will assist in generating a common rule
for rule based SRAF. Method to extract the rule from the models will first be discussed. Model assisted rule
based SRAF will be applied to 3Xnm DRAM contact. Evaluation and analysis of the simulated and actual
wafer result will be discussed. Our wafer result showed that by applying Model assisted rule based SRAF
showed nearly equal performance to models based SRAF with clearly better stability and mask fabrication
Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout
correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in
EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated
PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real
device is measured experimentally with real device layout with clearing pads in it.
Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount
of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.
In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared
and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at
IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to
simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured
and compared with simulation result to match the predictability of the simulation tool.
Shadowing test comparison of wafer to simulation showed that simulation with resist model
showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within
2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error
RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher
accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist
model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool
showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and
shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using
EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.
One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography.
In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirk's disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.
Generally, rule based optical proximity correction (OPC) together with conventional illumination is used for contact layers, because it is simple to handle and processing times are short. As the design rule is getting smaller, it becomes more difficult to accurately control critical dimension (CD) variation because of influence by nearby contact holes pattern. Especially, random contact hole shows greater amount of CD difference between X and Y direction compared to array contact holes. Several resolution enhancement techniques (RET) were used to resolve this kind of problem, but didn't meet the overall expectations.
In this paper, we will present the results for novel contact hole model-based OPC for sub 60nm memory device. First, model calibration method will be proposed for contact holes pattern, which utilizes two thousands of real contact holes pattern to improve model accuracy in full chip. Second, verification method will be proposed to check weak points on full chip using model based verification. Finally, method for further enhancing CD variation within 5nm for model based OPC will be discussed using Die-to-Database Verification.
As the semiconductor feature size continues to shrink, electrical resistance issue is becoming one of the
industry's dreaded problems. In order to overcome such problem, many of the top semiconductor manufacturers have
turned there interest to copper process. Widely known, copper process is the trench first damascene process which
utilize dark tone mask instead of widely used clear tone mask. Due to unfamiliarity and under development of dark tone
mask technology compared to clear tone mask, many have reported patterning defect issues using dark tone mask.
Therefore, necessity of DFM for design that meets both dark and clear tone is very large in development of copper
process based device.
In this study, we will propose a process friendly Design For Manufacturing (DFM) rule for dual tone mask.
Proposed method guides the layout rule to give same performance from both dark tone and clear tone mask from same
design layout. Our proposed method will be analyzed on photolithography process margin factors such as Depth Of
Focus (DOF) and Exposure Latitude (EL) on sub 50nm Flash memory interconnection layer.
As the semiconductor industry continues progressing toward increasingly complex and
unforgiving processes of device shrinkage and shorter duration of device development, many
industry participants from photo-lithography are taking interest in material and structure of the
photolithography mask. Due to shorter wavelength of the source laser and device technology
ranging around the order of magnitude for the source laser wavelength (ArF), the difference in mask
material and structure shows greater performance difference then larger technology node. Especially
around 50nm and beyond, many industry followers are reporting better performance from different
types of mask then previously used.
In this study, we will analyze the effect of the photo lithography mask material for sub
50nm device, in development perspective. Two major types of mask will be evaluated on the scale
of device development. Effects such as Mask Error Effect Factor (MEEF), Depth of Focus (DOF),
Exposure Latitude (EL) and Critical Dimension Uniformity (CDU) will be analyzed for both binary
and attenuated phase shifted mask under different process condition. Also, we will evaluate the
comparison result for application on development of sub 45nm device.
An epidemic for smaller node has been that, as the device architecture shrinks, lithography process requires
high Numerical Aperture (NA), and extreme illumination system. This, in turn, creates many lithography problems such
as low lithography process margin (Depth of Focus, Exposure Latitude), unstable Critical Dimension (CD) uniformity
and restricted guideline for device design rule and so on. Especially for high NA, extreme illumination such as
immersion illumination systems, above all the related problems, restricted design rule due to forbidden pitch is critical
and crucial issue. This forbidden pitch is composed of numerous optical effects but majority of these forbidden pitch
compose of photo resist residue and these residue must be removed to relieve some room for already tight design rule.
In this study, we propose automated algorithm to remove photo resist residue due to high NA and extreme
illumination condition. This algorithm automatically self assembles assist patterns based on the original design layout,
therefore insuring the safety and simplicity of the generated assist pattern to the original design and removes any resist
residue created by extreme illumination condition. Also we tested our automated algorithm on full chip FLASH
memory device and showed the residue removal effect by using commercial verification tools as well as on actual test
As the design rule shrinks to its natural limit, reduction in lithography process margin and high Critical
Dimension (CD) error gives rise to use of many Resolution Enhancement Techniques (RET). Recently, one the popular
RET method to solve the above problem is polarized illumination. It is used to enhance the reduced lithography process
margin and enhance CD uniformity. Polarization lithography basically uses one sided polarized light source. Therefore
process margin increases for smaller design rule patterns. In this paper, we will present the results for polarized
illumination based Optical proximity Correction (OPC) for sub-60nm memory device. First, models for polarization
based and un-polarization based method will be compared for its model accuracy. Second, the process margin
improvement for polarized and un-polarized illumination will be compared and analyzed for poly layer of sub-60nm
memory device. Finally, method for further enhancing CD error within 5% for polarized OPC model will be discussed.
Over the last couple of years, Design For Manufacturability (DFM) has progressed from concept to practice.
What we thought then is actually applied to the design step to meet the high demand placed upon very high tech devices
we make today. One of the DFM procedures that benefit the lithography process margin is generation of dummy
patterns. Dummy pattern generated at design step enables stable yet high lithography process margin for many of the
high technology device. But actual generation of the dummy pattern is very complex and risky for many of the layer
used for memory devices. Dummy generation for simple pattern layers such as Poly or Isolation layer is not so difficult
since pattern composed for these layers are usually 1 dimensional or very simple 2 dimensional patterns. But for
interconnection layers that compose of complex 2 dimensional patterns, dummy pattern generation is very risky and
requires lots of time and effort to safely place the dummy patterns.
In this study, we propose simple self assembled dummy (SAD) generation algorithm to place dummy pattern
for the complex 2 dimensional interconnection layers. This algorithm automatically self assembles dummy pattern
based on the original design layout, therefore insuring the safety and simplicity of the generated dummy to the original
design. Also we will evaluate SAD on interconnection layer using commercial Model Based Verification (MBV) tool to
verify its applicability for both litho process margin and DFM perspective.
The dawn of the Sub 100nm technology has brought many new exciting challenges for lithography process such as Immersion, OPC, asymmetry illumination, and so on. But, these new technology brought about new problems we face today due to shrinkage of the feature size. Some of the problems such as PR defect, ID bias and Mask Error Factor(MEF) are very important, but the most critical of all for lithography engineer is low process margin created by these technologies.
In this study, we will be presenting the result of the Illumination based assist feature that enhances the lithography process margin for both Exposure Latitude (EL) and Depth Of Focus (DOF), while retaining safety of the scum generation by positioning the assist feature proportional to the illumination for 60nm device. Also, by automatically generating illumination based assist feature on the peripheral region of the mask, we will show that it levels the Critical Dimension (CD) uniformity for pattern of the same dimension located at both cell and peripheral region of the mask. Results will be tested on the mask feature size of 60nm and will be analyzed for both process margin and CD uniformity.
The contact hole patterning has been huge challenge in the photolithography since sub-100nm node device. There are many difficulties for NA (Numerical Aperture) and illumination optimization, especially since dense and sparse contact holes are mixed in the same mask. The high NA and OAI (Off Axis Illumination) have strong improvements for pattern fidelity and process margin in case of dense contact holes but DoF (Depth of Focus) margin is a problem for sparse patterns. The lithography engineers have two ways to overcome these contact holes patterning problems. The one is using the resist techniques such as resist thermal flow, SAFIER (Shrink Assist Techniques for Enhanced Resolution), RELACS (Resolution Enhancement Lithography Assisted by Chemical Shrink) and the other is optimizing illumination and mask layout such as SRAF (Sub Resolution Assist Feature), OAI and PSM (Phase Shift Mask), double exposure. This paper will discuss contact hole patterning results using a combination OAI and SRAF with KrF.
As the design rule of device shrinks down, it is difficult to enlarge the process window, especially DOF (Depth of Focus). It has shown good results in resolution issues with short wavelength, high NA aperture and several RET (Resolution Enhancement Technique) like special illuminator and mask techniques and so on. But it needs to be challenged for DOF process window in contact / via process having various pitch and pattern location. It is a key point in sub 100nm process development and product. It is demonstrated that focus scan method is effective for DOF improvement in contact and via layers. Focus Scan method is one of the focus drilling techniques; it is realized to tilt wafer stage so that the same point on the wafer field can be exposed in limited continual focus range using multiple focal planes through the slit of scanner tool. In this study, confirmation was inspected for simulation and wafer evaluation for focus scan effects in view of process feasibility. DOF increased over 50% with focus scan in contact mask process even though there are several issues to be solved and considered. Energy Latitude (EL) decreased a little by image contrast drop, but if we consider the process window for evolution of device, it is relatively enough for process. OPC or Bias tuning is needed for application in contact layer having various pitch and location, and overlay issues are needed to confirm for each illuminator. From these experiments, it is found that DOF margin can easily be enhanced using focus scan method. Also some fine tuning is required to adequately use this method on production devices.
In a world where Sub100nm lithography tool is an everyday household item for device makers, shrinkage of the device is at a rate that no one ever have imagined. With the shrinkage of device at such a high rate, demand placed on Optical Proximity Correction (OPC) is like never before. To meet this demand with respect to shrinkage rate of the device, more aggressive OPC tactic is involved. Aggressive OPC tactics is a must for sub 100nm lithography tech but this tactic eventually results in greater room for OPC error and complexity of the OPC data. Until now, Optical Rule Check (ORC) or Design Rule Check (DRC) was used to verify this complex OPC error. But each of these methods has its pros and cons. ORC verification of OPC data is rather accurate "process" wise but inspection of full chip device requires a lot of money (Computer , software,..) and patience (run time). DRC however has no such disadvantage, but accuracy of the verification is a total downfall "process" wise. In this study, we were able to create a new method for OPC data verification that combines the best of both ORC and DRC verification method. We created a method that inspects the biasing of the OPC data with respect to the illumination condition of the process that's involved. This new method for verification was applied to 80nm tech ISOLATION and GATE layer of the 512M DRAM device and showed accuracy equivalent to ORC inspection with run time that of DRC verification.
Double Exposure Technology (DET) is one of the main candidates for expanding the resolution limit of current lithography tool. But this technology has some bottleneck such as controlling the CD uniformity and overlay of both mask involved in the lithography process. One way to solve this problem and still maintain the resolution advantage of DET is using spacers. Patterning with a spacer not only expands the resolution limit but also solves the problems involved with DET. This method realizes the interconnection between the cell and peripheral region by "space spacer" instead of "line spacer" as usually used. Spacer process involves top hard mask etch, nitride spacer, oxide deposition, CMP, and nitride strip steps sequentially. Peripheral mask was additionally added to realize the interconnection region. With the use of spacers, it was possible to realize the NAND flash memory gate pattern with less than 50nm feature only using 0.85NA (ArF).
In recent years, more burden is placed on OPC(Optical Proximity effect Correction) and ORC(Optical Rule Check) like never before due to low process margin caused by adoption of "Low K1" technology on lithography process. Normally, chip is composed of cell, core and periphery regions. Each of these regions has different characteristics patterning wise but usually the region with high density has much more chance for pinch, bridge or killing error and also has small process window. So verification of OPCed data must be highly accurate with fast operation speed. In this paper we developed full chip based ORC(Optical Rule Check)which satisfies both need, accuracy and speed. The result of pinch, bridge and small process window verification of Hybrid ORC will be shown followed by comparison of rule and model ORC methods.