A novel and simple circuit implementation of trap centres in GaAs and GaN HEMTs, MESFETs and HFETs is presented.
When included in transistor models it explains the potential-dependent time constants seen in the circuit manifestations of
charge trapping, being gate lag and drain overshoot. The implementation is suitable for both time- and harmonic-domain
simulations. The trap-centre model is based on Shockley-Read-Hall (SRH)1 statistics of the trapping process. It also
accommodates carrier injection from other important device effects, such as impact ionization and light sensitivity.
In the model, the ionization charge of the trap centre is represented by the charge in a capacitor. The potential across the
capacitor is proportional to the potential across the region of the trap centre in the semiconductor. It is positive or negative
depending on the polarity of the ionization charge - electrons or holes. When included in a transistor model, this potential
is added to the gate potential that controls the drain-current description.
The capacitor is charged or discharged by two opposing currents that are functions of the ionization potential and
temperature: one models charge emission; and the other, which is also controlled by an external potential and injected
current, models charge capture. The external potential is typically a linear function of a transistor's terminal potentials.
The injection current can model charge generated by light or by holes from impact ionization.
The four parameters for the model are simply the signed potential of the trap centre when fully ionized, the time
constant for charge emission at a specific temperature, the injection-current sensitivity, and the activation energy of the
emission process. The latter is used to predict the temperature dependence of the emission rate. The capture rate is
determined within the model by an exponential function of the external potential that controls capture. Thus the model
elegantly predicts asymmetry between trap charging and discharging rates. The model accounts for variation in emission
and capture rates with temperature, which is shown to vary significantly over typical transistor operating ranges.
High speed frequency dividers are critical parts of frequency synthesisers in wireless systems. These dividers
allow the output frequency from a voltage controlled oscillator to be compared with a much lower external
reference frequency that is commonly used in these synthesisers. Common trade-offs in high frequency dividers
are speed of division, power consumption, real estate area, and output signal dynamic range. In this paper
we demonstrate the design of a high frequency, low power divider in 0.18 µm SiGe BiCMOS technology. Three
dividers are presented, which are a regenerative divider, a master-slave divider, and a combination of regenerative
and master-slave dividers to perform a divide-by-8 chain. The dividers are used as part of a 60 GHz frequency
synthesizer. The simulation results are in agreement with measured performance of the regenerative divider.
At 48 GHz the divider consumes 18 mW from a 1.8 V supply voltage. The master-slave divider operates up to
36 GHz from a very low supply voltage, 1.8 V. The divide-by-8 operates successfully from 40 GHz to 50 GHz.
This paper looks at the problems associated with pulsed testing of GaN and GaAs HEMTs and its use in examining the charging and discharging times of the various traps that affect conduction. A particular problem is that the RF behaviour of these transistors varies with the state of charge of the traps. This is a concern for a large class of applications where the usage pattern is comparable to the time constants of the traps. Such classes include the intermittently-switched front ends of 802.11 and mobile telephone circuits. The conventional approach with pulsed testing is to sit at a bias point for a sufficiently long time and then to pulse to characteristic voltages very quickly before returning to the bias. If the pulsing to the applied characteristic voltages is much faster than the time constants of the traps of the transistor, then the characteristic measured will reflect the state of charge of the traps for the bias point. Our approach here is to perform a series of characteristic measurements as the bias and trap charge-state change. Each characteristic is measured too quickly to affect the trapped charge significantly. The set of characteristics then reflects the changing nature of the transistor's bias and state of charge of its traps.
Conference Committee Involvement (2)
Microelectronics: Design, Technology, and Packaging III
5 December 2007 | Canberra, ACT, Australia
Microelectronics: Design, Technology, and Packaging II