Machine learning (ML) has become increasingly powerful and several recent works have demonstrated the capa- bility of neural networks to achieve performance gains for lithography applications. Much of the general literature on neural networks involves image classification. Application of neural networks to lithography requires increased scrutiny. How far can such a system be trusted, and how should we respond if the system fails? Neural net- works can appear inscrutable and we lack understanding of why these systems generalize so well. On the other hand, the benefits neural networks appear to offer, in terms of reduced runtime or more accurate models, are compelling. This work will illustrate how two techniques, the Information Bottleneck (IB) and t-Distributed Stochastic Nearest Neighbors (t-SNE), that can improve our understanding of how neural networks work. We will use a multilayer perceptron for a simple resist model implemented with neural networks. We will then discuss how visualiztion methods can help assess the readiness of a neural network for a task, or help diagnose potential causes of failure.
With constant shrinking of device critical dimensions (CD), the quality of pattern transfer in IC fabrication depends on the etch process and the exposure process fidelities, and the interaction of lithographic and etching processes is no longer negligible. Etch effect correction with accurate models has become an important component in optical proximity correction (OPC) modeling and related applications. It is now commonly accepted that the lithographic and etch effects should be modeled and corrected in a sequential and staged way: a resist (or lithographic) model should be created and used for lithographic effect compensation, and an etch model should be created and used for etch effect compensation. However, there can be various degrees of separation of these two modeling stages. In order to optimally capture the significant variation in the post-development resist patterns and post-etching patterns, it is helpful to integrate these two processes together for the OPC model calibration practice. In this paper, we analyze the integrated simulation approach in OPC modeling where the entire resist model information is made fully accessible in the etch modeling stage to allow the possibility of resist and etch co-optimization, e.g. through adjusting the resist model to optimally fit the etch data. Furthermore, the integrated simulation technique is integrated into a verification flow to simplify the conventional staged flow.
A single compact resist model capable of predicting 3D resist profile is strongly demanded for the advanced technology
nodes to avoid the potential hotspots due to imperfect resist pattern shape and its lack of resistance in the subsequent
etch process. In this work, we propose a resist 3D (R3D) compact model that takes acidz-diffusion effect into account.
The chemical reaction between acid and base along z-direction is treated as second order effect that is absorbed into the
anisotropic diffusion length as a fitting parameter. Meanwhile, the resist model in the x-y wafer plane is still kept in
general by applying the compact solution of 2D reaction-diffusion equation. In order to have the 2D contour
predictability at arbitrary resist height, calibration from entire 3D data (CDs at several heights) areconducted
simultaneously witha single cost function so that the R3D compact model is described by a common set of resist free
parameters and threshold for all resist heights. With the low energy approximation, the acid z-diffusion effect is
equivalent to a z-diffused TCC that takes the form of linear combination of pure optical TCCs sampled at discrete
image-depth which can be pre-calculated. With this benefit, the R3D compact model offers a more physical approach but
adds no runtime concern on the OPC and verification applications. The predicted resist cross-section profiles from our
test patterns are compared those computed with rigorous lithography simulator SLITHO and show very good matching
results between them. The demonstration of the AF printability check from the predicted cross-section profile at AF
indicates the success of our R3D compact model.
Self-aligned double patterning (SADP) lithography is a leading candidate for 14nm node lower-metal layer fabrication. Besides the intrinsic overlay-tolerance capability, the accurate spacer width and uniformity control enables such technology to fabricate very narrow and dense patterns. Spacer-is-dielectric (SID) is the most popular flavor of SADP with higher flexibility in design. In the SID process, due to uniform spacer deposition, the spacer shape gets rounded at convex mandrel corners, and disregarding the corner rounding issue during SID decomposition may result in severe residue artifacts on device patterns. Previously, SADP decomposition was merely verified by Boolean operations on the decomposed layers, where the residue artifacts are not even identifiable. This paper proposes a model-based verification method for SID decomposition to identify the artifacts caused by spacer corner rounding. Then targeting residue artifact removal, an enhanced SID decomposition flow is introduced. Simulation results show that residue artifacts are removed effectively through the enhanced SID decomposition strategy.
Extreme ultraviolet (EUV) lithography is one of the leading technologies for 16nm and smaller node device patterning.
One patterning issue intrinsic to EUV lithography is the shadowing effect due to oblique illumination at the mask and
mask absorber thickness. This effect can cause CD errors up to a few nanometers, consequently needs to be accounted
for in OPC modeling and compensated accordingly in mask synthesis. Because of the dependence on the reticle field
coordinates, shadowing effect is very different from the traditional optical and resist effects. It poses challenges to
modeling, compensation, and verification that were not encountered in tradition optical lithography mask synthesis.
In this paper, we present a systematic approach for shadowing effect modeling and model-based shadowing
compensation. Edge based shadowing effect calculation with reticle and scan information is presented. Model calibration
and mask synthesis flows are described. Numerical experiments are performed to demonstrate the effectiveness of the
A technique traditionally used for optical proximity correction (OPC) is extended to include topography
proximity effects (TPE). Central to this is a thin-mask imaging model capable of addressing very large areas.
This compact model being compatible with traditional fast imaging models used in OPC can then be used in
standard correction approaches, compensating for both the optical proximity effects and wafer topography
proximity effects. Model origin and model form are considered along with calibration process. Capturing
ability and performance of the model are numerically evaluated on a number of test patterns. The performance
of the model is close to that of models used in the planar case.
This paper presents a novel mask corner rounding (MCR) modeling approach based on Synopsys' Integrated Mask and
Optics (IMO) modeling framework. The point spread functions of single, double, and elliptical Gaussians are applied to
the IMO mask kernels to simulate MCR effects. The simulation results on two dimensional patterns indicate that the
aerial image intensity variation is proportional to the MCR induced effective area variations for single type corners. The
relationship may be reversed when multiple types of corners exist, where the corners close to the maximum intensity
region have a greater influence than others. The CD variations due to MCR can be estimated by the effective area
variation ratio and the image slope around the threshold. The good fitting results on line-end patterns indicate that the
ΔCD is the quadratic function of the Gaussian standard deviations. OPC modeling on 28nm-node contacts shows that
MCR has significant impact on model fitting results and process window controls. By considering the real mask
geometry effects and allowing in-line calibration of model parameters, the IMO simulation framework significantly
improves the OPC model accuracy, and maintains the calibration speed at a good level.
Small feature sizes down to the current 45 nm node and precision requirements of patterning in 193 nm
lithography as well as layers where the wafer stack does not allow any BARC require - not only correction of
optical proximity (OPC) effects originating from mask topography and imaging system, but also correction of
wafer topography proximity (WTPC) effects as well. In spite of wafer planarization process steps, wafer
topography (proximity) effects induced by different optical properties of the patterned materials start playing
a significant role, and correction techniques need to be applied in order to minimize the impact.
In this paper, we study a methodology to create fast models intended for effective use in OPC and WTPC
procedures. In order to be short we use the terms "OPCWTPC modeling" and "OPCWTPC models" through
the paper although it would be more correctly to take the terms "mask synthesis modeling" and "mask
A comprehensive data set is required to build a reliable OPC model. We present a "virtual fab" concept using
extensive test pattern sets with both 1D and 2D structures to capture optical proximity effects as well as wafer
A rigorous lithography simulator taking into account exposure tool source maps, topographic mask effects as
well as wafer topography is used to generate virtual measurement data, which are used for model calibration
as well as for model validation.
For model building, we use a two step approach: in a first step, an OPC model is built using test patterns on a
planar, homogenous substrate; in a second step a WTPC model is calibrated, using results from simulated test
patterns on shallow trench isolation (STI) layer. This approach allows building models from experimental
data, including hybrid approaches where only experimental data from planar substrates is available and a
corresponding OPC model for the planar case can be retrofitted with capabilities for correcting wafer
We analyze the relevant effects and requirements for model building and validation as well as the
performance of fast WTPC models.
Photolithography on reflective surfaces with topography can cause overexposure in some areas in the photoresist,
resulting in undesired critical dimension (CD) variations in the printed patterns. Using bottom anti-reflective coatings
(BARCs) will reduce the severity of the problem. However it is not a preferred solution in some situations due to added
process complexity, such as the case of implant blocking layer patterning. This topography proximity effect (TPE) has
been ignored in the mask synthesis flow for the 45nm and larger nodes due to its relatively small impact to the CDs.
When the device critical length reaches 32nm and lower, the variations on the implant layer caused by underlying
topography becomes more and more an issue and need to be addressed properly. In order to do that, simulation with nonplanar
stack is required. The available tools for photolithography simulation with wafer topography, such as Synopsys'
Sentaurus Lithography (S-Litho), usually adopt a rigorous approach based on the solution of the Maxwell equations and
unsuitable for full chip optical proximity correction (OPC) due to their prohibitively long runtimes. A fast method for
TPE modeling is needed to make full chip TPE correction feasible.
In this paper, we propose a computationally fast approximate method that captures TPE well. It enables fast model
calibration and full chip implant layer mask correction, and fits in the current OPC flows easily. We validate the
method's effectiveness by comparing its simulation results with those produced by Sentaurus Lithography. We also
show how it helps implant layer mask synthesis that takes TPE from previous layers into consideration.
A thin membrane called a pellicle is commonly used to protect the mask from contamination. The thickness of the
pellicle material is usually optimized at normal incident angle to minimize the thin film optics interference effect by
cancellation of the reflected light from the top ambient/pellicle interface with the reflected light from the bottom
pellicle/ambient interface. In previous lithography generations the maximum angle collected by the projection lens (NA)
was low, hence the normal incidence approach was valid, and the transmission loss for the non-normal incident angles
was minor and ignored. With modern hyper-NA imaging for 45nm and smaller nodes, this transmission attenuation
becomes larger. The more stringent CD error budget of these technology nodes demands that this effect should not be
In this paper, we present a modeling framework that takes into consideration the high angle pellicle effects. Taking the
pellicle's polarization state dependent transmission data, which can be measured or computed with a rigorous simulator,
we first present the pellicle transmission property as Jones matrices on the pupil plane, and then incorporate pellicle
modeling into the existing vector model for lithography imaging computation. Existing modeling software for modelbased
OPC/RET tools is easily enhanced to include pellicle modeling. Using Synopsys' OPC/RET modeling software
ProGen, we investigate the necessity of pellicle effect modeling for mask synthesis for 45 nm and smaller nodes.
Numerical experiments are performed to study the impact of illumination polarization on the accuracy of lithography
simulation and the quality of OPC results.
High NA and Ultra-High NA (NA>1.0) applications for low k<sub>1</sub> imaging strongly demand the adoption of polarized
illumination as a resolution enhancement technology since proper illumination polarization configuration can greatly
improve the image contrast hence pattern printing fidelity and the effectiveness of optical proximity correction (OPC).
However, current OPC/RET modeling software can only model the light source polarization of simple types, such as TE,
TM, X, Y, or sector polarization with relatively simple configuration. Realistic polarized light used in scanners is more
complex than the aforementioned simple ones. As a result, simulation accuracy and quality of the OPC result will be
compromised by the simplification of the light source polarization modeling in the traditional approach. With ever
shrinking CD error budget in the manufacturing of IC's at advanced technology nodes, more accurate and
comprehensive illumination source modeling for lithography simulations and OPC/RET is needed. On the other hand,
for polarized illumination to be fully effective, ideally all the components in the optical lithography system should not
alter the polarization state of light during its propagation from illuminator to wafer surface. In current OPC modeling
tools, it is typically assumed that the amplitude and polarization state of the light do not change as it passes through the
projection lens pupil, i.e. the polarization aberration of projection lens pupil is ignored. However, in reality, the
projection lens pupil of the scanner does change the amplitude and the polarization state to some extent, and ignorance
of projection pupil induced polarization state and amplitude changes will cause CD errors un-tolerable at the 45nm
device generation and beyond.
We developed an OPC-deployable modeling approach to model arbitrarily polarized light source and arbitrarily
polarized projection lens pupil. Based on polarization state vector descriptions of a general illumination source, this
modeling approach unifies optical simulations of unpolarized, partially polarized, and completely polarized
illuminations. The polarization aberration imposed by the projection lens pupil is modeled via Jones matrix format, and
it is applicable to arbitrary polarization aberrations imposed by any components in the lithography system that can be
characterized in Jones matrix format. Numerical experiments were performed to study CD impact from illumination
polarization and projection lens pupil polarization aberrations, and up to several nanometers impact on optical proximity
effect (OPE) was observed, which is not negligible given the extremely stringent CD error budget at 45nm node and
beyond. Based on an experimentally measured Jones matrix pupil which intrinsically provides a much better
approximation to the physical scanner projection pupil, we propose a more physics-centric methodology to evaluate the
optical model accuracy of OPC simulator.
The concept of focus blur encompasses the effect of laser bandwidth longitudinal
chromatic aberration and scanner stage vertical vibration. The finite bandwidth of
excimer laser source causes a corresponding finite distribution of focal planes in a range
of 100nm or larger for the optical lithography system. Similarly, scanner vertical stage
vibration puts the wafer in a finite distribution of focal planes. Both chromatic aberration
and vertical stage vibration could introduce significant CD errors, hence can no longer be
ignored in current lithography processes development and OPC development that require
CD control within a few nanometers. We developed several methodologies to model the
laser chromatic aberration and vertical stage vibration in OPC (Optical Proximity
Correction) modeling tool. Extensive simulations were done to calculate chromatic
aberration and vertical stage vibration focus blur's impact on lithography patterning for a
variety of test structures. Chromatic aberration and vertical stage vibration focus blur
effect was further included as an regression term in experimental OPC model calibration
to capture its impact on litho patterning, and significant benefit to OPC model calibration
Recent research has shown that properly polarized light source enhances image contrast in photolithography for
manufacturing integrated circuit (IC) devices, thus improves the effectiveness of optical proximity correction (OPC) and
other resolution enhancement techniques (RET). However, current OPC/RET modeling software can only model the
light source polarization of simple types, such as TE, TM, X, Y, or sector polarization with relatively simple
configuration. Realistic polarized light used in scanners is more complex than the aforementioned simple ones. As a
result, simulation accuracy and quality of the OPC result will be compromised by the simplification of the light source
polarization modeling in the traditional approach. With ever shrinking CD error budget in the manufacturing of IC's at
advanced technology nodes, more accurate and comprehensive light source modeling for lithography simulations and
OPC/RET is needed.
In this paper, we present a modeling framework that takes arbitrarily polarized light source. Based on polarization state
vector descriptions of the light source, it unifies optical simulations of unpolarized, partially polarized, and completely
polarized illuminations. We built this framework into Synopsys' OPC modeling tool ProGen. Combined with ProGen's
existing capability to handle vectorial aberration by the projection lens, large angle effects due to high NA, and thin film
effects, this framework represents a general vectorial model for optical imaging with the state-of-the-art scanners.
Numerical experiments were performed to study CD impact of various illumination polarization modeling schemes in
the context of OPC/RET.
Topographic mask effects can no longer be ignored at technology nodes of 45 nm, 32 nm and beyond. As
feature sizes become comparable to the mask topographic dimensions and the exposure wavelength, the popular
thin mask model breaks down, because the mask transmission no longer follows the layout. A reliable mask
transmission function has to be derived from Maxwell equations. Unfortunately, rigorous solutions of Maxwell
equations are only manageable for limited field sizes, but impractical for full-chip optical proximity corrections
(OPC) due to the prohibitive runtime. Approximation algorithms are in demand to achieve a balance between
acceptable computation time and tolerable errors.
In this paper, a fast algorithm is proposed and demonstrated to model topographic mask effects for OPC
applications. The <i>P</i>r<i>o</i>Gen <i>To</i>pographic <i>Ma</i>s<i>k</i> (POTOMAC) model synthesizes the mask transmission functions
out of small-sized Maxwell solutions from a finite-difference-in-time-domain (FDTD) engine, an industry leading
rigorous simulator of topographic mask effect from SOLID-E. The integral framework presents a seamless solution
to the end user. Preliminary results indicate the overhead introduced by POTOMAC is contained within the same order of magnitude in comparison to the thin mask approach.
The upcoming 45nm device node is a point at which newer field-based (i.e., dense pixel-based) OPC simulation methods may begin to show advantages over sparse-sampling ("flash") simulation methods. Field-based simulation provides computational efficiencies in applications where a large number of model evaluation locations are needed, and where the simulated layout geometry is complex. Field-based simulation leverages computation in the frequency domain, whereas sparse-sampling methods operate in the space domain. Mathematically, both methods are equivalent but their respective numerical methods give rise to some implementation differences for OPC applications. These differences include different optimization strategies for hierarchical processing, and fine-grained feature symmetry control for critical matched-transistor circuits (such as SRAM, where noise margin is a fundamental device control issue). An optimum, field-based OPC solution will address these differences without compromising the performance benefits of field-based methods. In this paper we describe and compare the manufacturing implementation of flash-based and field-based OPC at the 45nm and 32nm device nodes
Liberal use of assist features of both tones is an important component of the 45nm lithography strategy for many
layers. These features are often sized at λ/4 on the mask or smaller. Under these conditions, formerly successful
approximations of the mask near field using boundary layer methods or domain decomposition methods break
down. Rigorous simulations of the mask near field must include a three-dimensional (3D) Maxwell's equation
analysis, but these computations are cost-prohibitive for full-chip OPC, RET, and lithographic compliance
The purpose of this paper is to describe a simple and computationally efficient method that can improve model
fidelity for 45nm assist features of either tone, while still retaining computational simplicity. While the model
lacks the generality of a rigorous solution of Maxwell' sequations, it can be well-anchored to the real physics by
calibrating its performance to a lithographic TCAD mask simulator. The approach provides a balanced tradeo.
between speed and accuracy that makes it a superior approach to boundary layer and domain decomposition
methods, while retaining the capability to realistically be deployed on a full-chip lithography simulation.
Immersion lithography has been accepted as the major breakthrough for enabling next generation deep subwavelength chip production. As it extends the resolution capability of optical lithography to the next technology node, it brings fresh challenges to resolution enhancement techniques (RET). Accurate lithography modeling becomes even more critical for RET at the sub-65nm nodes. On the other hand, immersion models need to be fully compatible within the context of existing optical proximity correction (OPC) flow.
With the hyper NA approach, modeling of immersion lithography requires full vector treatment of the electric fields in the propagating light wave. We developed a comprehensive vector model that considers not only the plane wave decomposition from the mask to the wafer plane, but also the light propagation through a thin film stack on the wafer. With the integration of this model into Synopsys OPC modeling tool ProGen, we have simulated and demonstrated several important enhancements introduced by immersion. In the mean time, the modeling and correction flow for immersion is completely compatible with the current OPC infrastructure.
The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman <i>et al.</i> in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.
Using a polarized illumination source is a promising RET technique for improvement of wafer printability for features of 65 nm and below. Polarization effects could be considered in several different stages of lithography modeling and simulation. For example, light propagation in thin films, wave superstition and interference in the thin film stack, and mask-induced polarization all deserve special attention and delicate treatment because TE and TM waves have different behaviors through these stages. In this paper we consider effects of polarized illumination in photo resist, using the Kirchhoff approximation for masks. We discuss some theoretical aspects of our vector modeling methods and show an example of simulation for polarized illumination effects.
An accurate process model is the linchpin of model-based Optical Proximity Correction (OPC) and Resolution Enhancement Technique (RET) synthesis. The accuracy of the resulting mask layout can be no better than that of the model. Relatively good, first-principle mathematical models exist for some process steps, such as aerial image formation, but resulting silicon is a combination of many effects, including those less well understood. Accuracy can be assured only with models anchored to observed phenomena. Process models are usually a combination of first principle elements and phenomenological components with the “right” degrees to freedom to fit the overall process. The key challenge in generating accurate models is to capture all process behavior over all conditions with a minimum number of empirical measurements. This means that models must extrapolate accurately from the specifics measured, and should be largely immune to empirical measurement noise. In this paper we describe a methodology in which to test model performance with respect to these criteria.
As an important resolution enhancement technique (RET), alternating aperture phase shift masks (AAPSM) has been widely adopted in 90 nm technology node and beyond. Mask topographical effect due to the 3D nature of the shifter features is becoming an increasingly important factor in lithography modeling. Rigorous 3D modeling of PSM is very computationally demanding thus impractical for full chip optical proximity correction (OPC). Here we introduce an alternative approach employing boundary layers to effectively approximate the 3D mask effect. We will present the model calibration versus real wafer data using the boundary layers and the corresponding OPC correction flow.
Model-based optical proximity correction (OPC) calculates pattern adjustments by simulating the layout with calibrated lithography and process models. OPC can only correct systematic lithography deviations, those error components that repeat chip to chip. OPC cannot compensate random deviation error components from unpredictable process variations, such as defocus and dose. However the ranges of variation from random effects is predictable, and OPC can optimize correction shapes to minimize this range where possible. Current techniques for supporting this optimization involve applying a set of models covering the range of expected process variations in defocus and exposure. Variation is assessed by comparing process corner-point model evaluations. Because there is a significant runtime cost simulating multiple process conditions, most production OPC jobs use a single, representative model (typically the "nominal" process condition) aided with rules and other heuristics to help handle process window effects.
In this paper the application of a new type of model that can be used to predict process variation with a single simulation call. The model involved in these studies targets pattern behavior as the focus offset deviates from the nominal focus setting. Used in conjunction with a nominal process model, this model can support process-window optimized OPC without the need for multiple models at various defocus settings. This model can also be used by itself to assess the defocus robustness of any configuration before or after OPC, thereby supporting efficient model-based layout verification.
Sub-resolution assist features (SRAFs) are non-printing features arranged on a mask layout to “assist” the lithographic performance of the lines intended to be printed on the wafer . SRAFs typically are narrow lines located adjacent to the target figure edges. Current practice is to synthesize SRAFs with a rule-based methodology where the assist feature placement is dictated by combinations of feature width and spacing parameters. Optical behavior with off-axis illumination is complex and requires an elaborate set of SRAF synthesis rules. Creating and maintaining a robust set of placement rules guaranteed to work properly for arbitrary configurations is very difficult. Socha, <i>et al</i>, have demonstrated that the optimum configurations for SRAFs can be derived from the aerial image of the target layout configuration . In this paper we show how SRAF synthesis can be optimally implemented in an OPC tool environment, leveraging lithography simulation.
Complex layout features, especially two-dimensional features such as jogs and corners, are susceptible to photoresist pinching and bridging, even with the use of Optical Proximity Correction. Some of these problems arise due to improper interpretation of the design intent when determining the correction targets. These targeting problems result in excessively aggressive correction in the vicinity of two-dimensional features. Compounding the problem is the propagation of the effects of aggressive correction into 1 dimensional pattern regions, resulting in oscillatory deviations from the correction target along one-dimensional edges. Current correction processes use rules and geometric approximations based on the feature's size to generate a curved target for OPC tools to reference during correction. A new model-based methodology is proposed that will utilize significantly more pattern information as well as process information to determine how a feature should be interpreted. The model-based target construction reacts to pitch and other geometric variations within the model's influence. This targeting methodology is therefore able to predict a realistic shape for two-dimensional feature based on all pattern information within model proximity. The model-based manipulation reduces pitch and other proximity related effects for two-dimensional features, especially at more aggressive process nodes.
As post-litho process effects account for a larger and larger portion of CD error budgets, process simulation terms must be given more weight in the models used for proximity correction. It is well known that for sub-90 nm processes resist and etch effects can no longer be treated as a small perturbation on a purely optical (aerial image) OPC model. The aerial image portion of the model must be combined in a more appropriate way with empirical terms describing resist and etch effects. The OPC engineer must choose a model form which links an optical component with a resist/etch component in a manner that balances efficiency, robustness and fidelity to the aerial image, among other factors. No single way of connecting litho and etch models is ideal in all cases; the best form of linkage depends on the particular litho and etch process to be simulated. In this paper, we provide practical guidelines for linking litho and etch components of a model, using a representative 70 nm process with a large etch bias as an example. This 70 nm case study, which is representative of many sub-90 nm processes that rely on etch to shrink critical features, presents special challenges for OPC modeling. For the process under study, lines were are printed in resist at 120 nm, and the litho model was verified via resist SEM measurements taken at the resist edge. Note that a thresholded aerial image is not well-characterized a distance 25 nm from the resist edge. This is roughly the distance the edge moves back due to the etch step. Although in some cases etch bias can be calculated from aerial image contrast, in general etch bias cannot be predicted from the aerial image because litho and etch are governed by different underlying physics. The model forms available for linking litho and etch range from the efficient “lumped” form, which combines litho and etch simulation in a single model, to a highly accurate two-stage form which separates the two components. In this paper we evaluate the following model forms for applicability to the 70 nm process under study: 1) Aerial image/load kernel combined (“lumped”) model form 2) Aerial image/rule offset “hybrid” model form 3) Separate litho and etch models (2-stage correction)
The challenges of the 65 nm node and beyond require new formulations of the compact convolution models used in OPC. In addition to simulating more optical and resist effects, these models must accommodate pattern distortions due to etch which can no longer be treated as small perturbations on photo-lithographic effects. (Methods for combining optical and process modules while optimizing the speed/accuracy tradeoff were described in “Advanced Model Formulations for Optical and Process Proximity Correction”, D. Beale et al, SPIE 2004.) In this paper, we evaluate new physics-based etch model formulations that differ from the convolution-based process models used previously. The new models are expressed within the compact modeling framework described by J. Stirniman <i>et al</i>. in SPIE, vol. 3051, p469, 1997, and thus can be used for high-speed process simulation during full-chip OPC.
The ever-increasing demand for shrinkage of IC device dimensions has been pushing the development of new technologies in micro lithography. Polarized illumination source is one of the emerging techniques in lithography to increase wafer printability, especially for 65 nm features and below. In the mean time, most RET techniques, which are showing more and more importance in lithography, are based on a highly accurate optical lithography model and simulator. Consequently, simulation and modeling tools for optical lithography may have to include the effects of source polarization in thin film stacks. In this paper we discuss some theoretical aspects of vector modeling methods that are utilized for polarization modeling and show results from Synopsys’ simulation tool Progen.
Immersion lithography has been regarded as the most viable contender to extend the resolution capability of optical lithography using 193nm wavelength. In parallel with the tremendous effort of overcoming the engineering challenges in immersion, support from modeling and simulations is strongly needed. Although immersion simulation has become available through a number of simulation tools, we need to investigate the model generation and its compatibility within the context of full-chip optical proximity correction (OPC).
In this paper, we will describe the physics of a full vector model that is necessary for the high NA optical modeling under immersion. In this full vector model, we consider not only the plane wave decomposition as light travels from the mask to wafer plane, but also the refraction, transmission and reflection of light through a thin film stack on the wafer. We integrated this comprehensive vector model into Synopsys OPC modeling tool ProGen. Through ProGen simulation results, we will discuss several important merits of immersion lithography, as well as the full portability of immersion models into OPC process flow.
Standard industry practice in model-based optical proximity correction is to use a single-stage model in which mask, optical projection, resist, and etch effects are lumped together [J.P. Stirniman, M.L. Rieger, SPIE Proc. Optical/Laser Microlithography X, Vol. 3051, p294, 1997.] Through the 130nm node, where optical projection and resist effects dominated proximity errors, the single-stage model approach has proven to be a convenient, accurate and efficient methodology. A disadvantage of this approach is its lack of modularity. If any one component of the process changes, a new lumped model must be built, usually by shooting a new set of test wafers from which to collect calibration data. Staged correction, in which corrections for different process steps are carried out sequentially, has become an appealing alternative to single-stage correction for the 130 nm node, 100 nm node and beyond. In addition to providing potential "mix and match" capabilities, the component corrections can be better optimized for unique behaviors in the constituent process steps. Thus, the overhead of sequencing through separate corrections can be offset by increased correction efficiency at each step to achieve accuracy equal to, or better than, that of a single stage correction with a lumped model. Separate corrections for etch and for litho/resist have been put into use in the industry and an additional stage for mask correction has also been considered.
In this paper we demonstrate advantages of staged correction over the traditional single-stage correction. Advantages and disadvantages of different staged correction flows will be examined, with particular emphasis on the flow where an etch correction is followed by a lithography correction.
Mask fabrication costs are significantly aggravated by OPC complexity. This increased complexity is presumably needed to accurately render 2-D configurations. The humble line-end is one of the most difficult 2-D configurations to print accurately, when considering process margin requirements and mask fabrication constraints. In this paper, the requirements for proximity corrected line-end structures will be explored and a pattern complexity metric will be proposed to compare relative mask cost versus line-end lithographic performance. Many types of correction shapes are available to improve process margin for line-ends. However, the cost of producing these various line-end configurations can vary dramatically. Using both a simple optical model to simulate line-end performance through focus offset and a cost metric based on fracture shots, a comparison of six types of lines ends for correction and process efficiency will be undertaken. Each of the six line-end corrections will attempt to produce equally effective silicon line-end shapes. Line-ends will be evaluated based on shortening (pullback), pinching, and bridging characteristics. Line-end lithographic behavior will be characterized through all process window boundary conditions. The objective of this study is to quantify the tradeoffs among three variables: mask cost, process-window robustness, and design tolerance margin. In addition, through the study of proximity effects on the various line-end types, the possibility of mixing expensive but high performance line-ends with simpler less aggressive line-ends to reduce reticle cost while maintaining or increasing correction fidelity will be studied.
Mask layouts with reticle enhancement techniques (RET) - including optical proximity correction (OPC), phase shift mask (PSM), Off-axis illumination, assist features (AF) - no longer closely resemble the design or wafer layouts. RET techniques are also applied with varying degrees of rigor to different portions of the layout, to constrain overall mask complexity while maintaining design requirements in critical areas. These factors make verifying RET mask layouts much more challenging. The simulation-based verification principle is straightforward: a wafer layout is simulated from the RET mask layout and compared to the intended design layout or 'target'. The required simulation technologies are mature and available today in commercial tools capable of handling large data files. The challenge in efficient verification is to establish comprehensive required for sub- wavelength lithography. Today, some simple criteria are inferred from the design or lithographic effects. Ideally, more specific information related to design 'intent' and tolerances should be built into the physical design for use in RET synthesis and verification, as well as in circuit and timing analysis. In this paper we explore emerging RET verification strategies that offer a high degree of flexibility and programmability. We will also illustrate how these techniques can take advantage of 'design intent' information embedded in the physical design, resulting in robust verification that is not confused by the complex tradeoffs required for today's sophisticated RET methodologies.
As k1 factors decline, optical proximity correction (OPC) treatments required to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, larger mask pattern databases. Intricate, dense mask-layouts increase mask writing time and cost. OPC employment within a growing number of lithography layers compounds the issue, leading to skyrocketing mask-set costs and long turn-times. ASIC manufacturing, where average chip life cycles consume less than 500 wafers, is particularly hard hit by elevated mask manufacturing costs. OPC increases mask data mainly by adding geometric detail - serifs, hammerheads, jogs, etc - to the design layout. The vertex count, a measure of shape complexity, typically expands by a factor of 2 to 5, depending on OPC objectives and accuracy requirements. OPC can also increase hierarchic data file size through loss of hierarchic compression. In this paper we outline several alternatives for reducing OPC data base size and for making OPC layout configurations friendlier to mask fabrication tools. An underlying assumption is that there is an optimum OPC treatment dictated by the behavior of the process, and that approximations to this ideal involve trade-offs with OPC accuracy. To whatever extent OPC effectiveness can be maintained while accuracy is compromised, mask complexity can be reduced.
This course provides background on supervised learning applied to microlithography. A primary goal of the course is to illustrate supervised learning, inference, and validation workflow to practitioners of microlithography, using datasets and problems with which they are familiar. Example applications will include photoresist models and inverse lithography models. Example model types include linear regressions, logistic classifiers and deep neural networks. Training methodology will utilize prepared datasets with Jupyter notebooks.