Ambipolar light-emitting field-effect transistors are fabricated with two different metals for the top-contact source and
drain electrodes; a low-work-function metal defining the channel for the source electrode and a high-work-function
metal defining the channel for the drain electrode. A thin film of polypropylene-co-1-butene on SiNx is used as the gate
dielectric on an n++-Si wafer, which functioned as the substrate and the gate electrode. Transport data show ambipolar
behavior. Recombination of electrons and holes results in a narrow zone of light emission within the channel. The
location of the emission zone is controlled by the gate bias.
We have used thermal treatment and rubbed polyimide alignment layers to produce large domains of poly(9,9-dioctylfluorene-co-bithiophene) alternating copolymer (F8T2). The direction of rubbing on the polyimide surface determines the orientation of these domains, allowing us to create thin-film transistors with channel lengths parallel and perpendicular to the liquid crystal polymer director. We showed that thermal annealing at temperatures ranging from 150 to 350°C modifies the polymer structure from an amorphous to ordered phase as observed by X-ray diffraction. Polarized light optical microscopy showed that this ordered phase is associated with very large ordered domains and corresponds to a thermotropic, nematic liquid-crystal phase. We investigated thermal annealing effects on both F8T2 structural ordering and the associated electrical properties of the thin film transistors (TFTs). Enhanced mobility of holes is observed with ordering. Field-effect mobility parallel to the polymer backbone is as much as 6.5 times greater than the perpendicular configuration.
The electrical properties of polymeric thin film transisitors (P-TFTs) based on poly(9,9-dioctylfluorene-co-bithiophene) alternating copolymer (F8T2) have been studied. Device performance was compared for amorphous silicon nitride deposited by LPCVD and PECVD techniques, aluminum oxide deposited by sputtering, titanium oxide deposited by sputtering, and thermal silicon oxide gate dielectrics. A heavily n-type doped crystalline silicon wafer coated with the desired gate dielectric was used. Photolithographic patterning of source/drain electrodes directly on top of the F8T2 layer is also discussed. The main conclusion from this work is that traps within the F8T2 define the conduction process within the device.