With the push toward the 32nm node, OPC modeling must respond in kind with additional accuracy enhancements.
One area of lithographic modeling that has basically gone unchecked is mask fidelity. Mask linearity is typically built
into the OPC model since the calibration data contain this information, but mask pattern fidelity is almost impossible to
quantify for OPC modeling. Mask fidelity is the rounding and smoothing of the mask features relative to the post-OPC
layout intent, and there is no robust metric available to quantify these effects. With the introduction of contour-based
model calibration, mask fidelity modeling is possible. This work evaluates techniques to quantify mask modeling and
methods to gauge the accuracy improvement that mask fidelity modeling would project into the lithographic process
using contour-based mask model calibration.
As design rules shrink, the goal for model-based OPC/RET schemes is to minimize the discrepancy between the
intended pattern and the printed pattern, particularly among 2d structures. Errors in the OPC design often result from
insufficient model calibration across the parameter space of the imaging system and the focus-exposure process
window. Full-chip simulations can enable early detection of hotspots caused by OPC/RET errors, but often these OPC
model simulations have calibration limitations that result in undetected critical hotspots which limit the process window
and yield. Also, as manufacturing processes are improved to drive yield enhancement, and are transferred to new
facilities, the lithography tools and processes may differ from the original process used for OPC/RET model calibration
conditions, potentially creating new types of hotspots in the patterned layer.
In this work, we examine the predictive performance of rigorous physics-based 193 nm resist models in terms of
portability and extrapolative accuracy. To test portability, the performance of a physical model calibrated using 1d data
from a development facility will be quantified using 1d and 2d hotspot data generated at a different manufacturing
facility with a production attenuated-PSM lithography process at k1 < 0.4. To test extrapolative accuracy, a similar test
will be conducted using data generated at the manufacturing facility with illumination conditions which differ
significantly from the original calibration conditions. Simulations of post-OPC process windows will be used to
demonstrate application of calibrated physics-based resist models in hotspot characterization and mitigation.
As design rules shrink, there is an unavoidable increase in the complexity of OPC/RET schemes required to enable
design printability. These complex OPC/RET schemes have been facilitating unprecedented yield at k1 factors
previously deemed "unmanufacturable", but they increase the mask complexity and production cost, and can introduce
yield-detracting errors. The most common errors are found in OPC design itself, and in the resulting patterning
robustness across the process window. Two factors in the OPC design process that contribute to these errors are a) that
2D structures used in the design are not sufficiently well-represented in the OPC model calibration test pattern suite, and
b) that the OPC model calibration is done only at the nominal process settings and not across the entire focus-exposure
This work compares two alternative methods for calibrating OPC models. The first method uses a traditional industry
flow for making CD measurements on standard calibration target structures. The second method uses 2D contour
profiles extracted automatically by the CD-SEM over varying focus and exposure conditions. OPC models were
developed for aggressive quadrupole illumination conditions (k1=0.35) used in 65nm- and 45nm-node logic gate
patterning. Model accuracy improvement using 2D contours for calibration through the process window is
demonstrated. Additionally this work addresses the issues of automating the contour extraction and calibration process,
reducing the data collection burden with improved calibration cycle time.
In order to achieve the necessary OPC model accuracy, the requisite number of SEM CD measurements has
exploded with each technology generation. At 65 nm and below, the need for OPC and/or manufacturing
verification models for several process conditions (focus, exposure) further multiplies the number of
measurements required. SEM-contour based OPC model calibration has arisen as a powerful approach to
deliver robust and accurate OPC models since every pixel now adds information for input into the model,
substantially increasing the parameter space coverage. To date however, SEM contours have been used to
supplement the hundreds or thousands of discreet CD measurements to deliver robust and accurate models.
While this is still perhaps the optimum path for high accuracy, there are some cases where OPC test
patterns are not available, and the use of existing circuit patterns is desirable to create an OPC model.
In this work, SEM contours of in-circuit patterns are utilized as the sole data source for OPC model
calibration. The use scenario involves 130 nm technology which was initially qualified for production with
the use of rule-based OPC, but is shown to benefit from model based OPC. In such a case, sub-nanometer
accuracy is not required, and in-circuit features can enable rapid development of sufficiently accurate
models to provide improved process margin in manufacturing.
Across-chip and across-wafer patterned linewidth variation (ACLV and AWLV respectively) as well as linewidth roughness (LWR) are key contributors to device performance variation. For polysilicon gate patterning, the linewidth control enabled by various phase-shift mask (PSM) design approaches is one of the key metrics in selecting the most manufacturable process. Embedded attenuated PSM (6% EAPSM), chromeless PSM (CPL) and alternating aperture PSM (AAPSM) designs were selected for comparison. Polysilicon wafers were exposed with 193nm lithography using these reticles, and then ACLV, AWLV and LWR were measured for each PSM process. The results are discussed and compared with other reticle design factors important for effective 65nm node patterning in production.
One of the consequences of low-k1 lithography is the discrepancy between the intended and the printed pattern, particularly in 2-D structures. Two recent technical developments offer new tools to improve manufacturing predictability, yield and control. The first enabling development provides the ability to identify the exact locations of lithography manufacturing "hot spots" using rigorous full-chip simulation. The second enabling development provides the ability to efficiently measure and characterize these critical locations on the wafer. In this study, hot spots were identified on four critical patterned layers of a 90nm-node production process using the Brion Tachyon 1100 system by comparing the design intent GDS-II database to simulated resist contours. After review and selection, the detected critical locations were sent to the Applied Materials OPC Check system. The OPC Check system created the recipes necessary to automatically drive a VeritySEM CD SEM tool to the hot spot locations on the wafer for measurements and analysis. Using the model-predicted hot spots combined with accurate wafer metrology of critical features enabled an efficient determination of the actual process window, including process-limiting features and manufacturing lithography conditions, for qualification and control of each layer.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
The practices needed to transfer the techniques to fabricate state-of-the-art optical sensor devices for aircraft applications from a laboratory environment to a production environmental have been analyzed. The experience gained from the development of several types of technologies as applied to sensors has been used as a baseline to generate procedural guidelines to begin the transfer of technology. Views on the design methods required during the development phase, in view of an inevitable production phase are presented.