EUV Infrastructure: EUV photomask backside cleaning
Applied Materials as first author: Bruce J. Fender, Dusty Leonhard, Hugo Breuer, Jack Stoof
ASML: My Phung Van, Rudy Pellens, Reinout Dekkers, Jan Pieter Kuijten
Due to electrostatic chucking of the backside of EUV masks, backside cleanliness in EUV lithography is an important factor. Contamination on the backside can cause damage to reticle (e-chuck), cross-contaminate to the scanner or cause local distortions in the reticle. Cleaning of the masks offers a solution to reduce the defectivity level on reticles. However, repeated cleaning on masks is known to have an impact on absorber, CD and reflectivity. Ideally, cleaning should occur without any alterations to the critical features on the front side of the mask. With the introduction of pellicles for EUV, there could be an additional drive for backside-only cleaning.
In this work the GuardianTM Technology is introduced that enables backside cleaning without any cleaning impact on the reticle front side through a protective seal at the outer edge of the mask. The seal protects the front side during the backside clean. The cleaning process encompasses a single-sided pre-clean oxygen plasma treatment of the mask surface, followed by sonic cleaning, and ending with a rinse and dry step. Separating the mask backside from front side enables:
• Backside cleaning without any cleaning impact on features on the mask front side.
• The isolation allows an aggressive cleaning of the backside to ensure defect removal.
• Processing of reticle with studs on the front side. This prevents unnecessary actions of stud removal and removal of the remaining glue after stud removal and subsequent gluing of the studs after cleaning.
Just before chucking of a reticle, the defectivity level on the mask is initially inspected with an in-scanner reticle backside inspection tool. The GuardianTM cleaning process is able to remove the vast majority of the cleanable defects that could impact scanner performance. Post GuardianTM clean interferometric microscope defect review reveals the remaining defects > 25-μm-PSL are ~78% are indent/damage and 11% are defects with insignificant height to impact scanner performance or cleanliness.
The semiconductor industry will soon be putting >=1.07NA 193nm immersion lithography systems into production for
the 45nm device node and in about three years will be putting >=1.30NA systems into production for the 32nm device
node. For these very high NA systems, the maximum angle of light incident on a 4X reticle will reach ~16 degrees and
~20 degrees for the 45nm and 32nm nodes respectively. These angles can no longer be accurately approximated by an
assumption of normal incidence. The optical diffraction and thin film effects of high incident angles on the wafer and
on the photomask have been studied by many different authors. Extensive previous work has also investigated the
impact of high angles upon hard (e.g., F-doped silica) thick (>700μm) pellicles for 157nm lithography, e.g.,.
However, the interaction of these high incident angles with traditional thin (< 1μm) organic pellicles has not been
widely discussed in the literature.
In this paper we analyze the impact of traditional thin organic pellicles in the imaging plane for hyper-NA
immersion lithography at the 45nm and 32nm nodes. The use of existing pellicles with hyper-NA imaging is shown to
have a definite negative impact upon lithographic CD control and optical proximity correction (OPC) model accuracy.
This is due to the traditional method of setting organic pellicle thickness to optimize normally incident light
transmission intensity. Due to thin film interference effects with hyper-NA angles, this traditional pellicle optimization
method will induce a loss of high spatial frequency (i.e., high transmitted angle) intensity which is similar in negative
impact to a strong lens apodization effect. Therefore, using simulation we investigate different pellicle manufacturing
options (e.g., multi-layer pellicle films) and OPC modeling options to reduce the high spatial frequency loss and its
impact.
Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds. The authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. Simulations on test structures have been calculated along with in photoresist simulations to predict the impact on process window capability. Test structures have been designed and fabricated into a functional test for evaluation. Process evaluations have been completed and exposure-defocus window calculated.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET's). The race to smaller and smaller geometry's has forced device manufacturers to k1's approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometries has forced device manufacturers to k1’s approaching 0.40. In this paper the authors will focus on the impact of mask exposure error factor (MEEF) through pitch for 120nm contacts with and without assist features. Experimental results show that although the addition of scatter bars improves depth of focus it has a negative effect on MEEF.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CPL) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. These new reticle technologies have many issues that are similar to simple binary masks. The authors have investigated the printability of defects in CPL mask technology. Programmed defects of various sizes and types have been simulated and printed for sub 100nm imaging. High resolution scanning electron microscopy has been used to characterize these defects and develop an understanding of size and type that prints. In this paper the authors will focus on image line end shortening and the impact of through dose and focus performance for very high NA ArF imaging. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. Various types of line ends have been evaluated for either straight CPL mask or hybrid type builds.
Each generation of semiconductor device technology drive new and interesting resolution enhancement technology (RET’s). The race to smaller and smaller geometry’s has forced device manufacturers to k1’s approaching 0.40. The authors have been investigating the use of Chromeless phase-shifting masks (CLM) exposed with ArF, high numerical aperture (NA), and off-axis illumination (OAI) has been shown to produce production worthy sub-100nm resist patterns with acceptable overlapped process window across feature pitch. There have been a number of authors who have investigated CLM in the past but the technology has never received mainstream attention due to constraints such as wet quartz etch during mask fabrication, limited approach to optical proximity correction (OPC), and exposure tool limitations such as on-axis illumination and too low of NA. With novel binary halftone OPC and a capable modern mask making process, it has become possible to achieve global and local pattern optimization of the phase shifter for a given layout especially for patterning features with dimension at sub-half-exposure wavelength. The authors have built a number of test structures that require superior 2D control for SRAM gate structures. In this paper the authors will focus on image process integration for the 65nm node. Emphasis on pattern layout, mask fabrication and image processing will be discussed. Furthermore, the authors will discuss defect printing, inspection and repair, mask error enhancement factor (MEEF) of 2D structures coupled with phase error, layout, and mask fabrication specifications.
Contact patterning for the 65nm device generation will be an exceedingly difficult task. The 2001 SIA roadmap lists the targeted contact size as 90nm with +/-10% CD control requirements of +/-9nm. Defectivity levels must also be below one failure per billion contacts for acceptable device yield. Difficulties in contact patterning are driven by the low depth of focus of isolated contacts and/or the high mask error (MEF) for dense contact arrays (in combination with expected reticle CD errors). Traditional contact lithography methods are not able to mitigate both these difficulties simultaneously. Inlaid metal trench patterning for the 65nm generation has similar lithographic difficulties though not to the extreme degree as seen with contacts. This study included the use of multiple, high transmission, 193nm attenuated phase shifting mask varieties to meet the difficult challenges of 65nm contact and trench lithography. Numerous illumination schemes, mask biasing, optical proximity correction (OPC), mask manufacturing techniques, and mask blank substrate materials were investigated. The analysis criteria included depth of focus, exposure latitude and MEF through pitch, reticle inspection, reticle manufacturability, and cost of ownership. The investigation determined that certain high transmission reticle schemes are strong contenders for 65nm generation contact and trench patterning. However, a number of strong interactions between illumination, OPC, and reticle manufacturing issues need to be considered.
The 65nm device generation will require steady improvements in lithography scanners, resists, reticles and OPC technology. 193nm high NA scanners and illumination can provide the desired dense feature resolution, but achieving the stringent overall 65nm logic product requirements necessitates a more coherent strategy of reticle, process, OPC, and design methods than was required for previous generations. This required integrated patterning solution strategy will have a fundamental impact on the relationship between design and process functions at the 65nm device node.
Semiconductor manufacturers are increasingly focusing on contact and via layers as the most difficult lithography pattern. Focus and exposure latitude, MEF, as well as iso-dense bias are challenges for contact patterning. This situation is only expected to worsen for the 65nm device generation where the 2001 SIA roadmap update lists the contact size as 90-100nm in 2004-2005. Thus, new contact pattern techniques with novel manufacturability are required. One possible avenue to meet these stringent process control requirements is the use of tri-tone high transmission attenuated phase shifting masks (tri-tone AttPSM) for the 65nm generation.
Multilayered SiN/TiN (9%-18%) EAPSM materials to manufacture advanced reticles were used in this investigation. Extensive study during the photomask processing (Front End and Back End) to access any issues related to the making of High %T tri-tone product types was performed.
Finally, the 2 prototype reticles were evaluated on a 193nm scanner (0.75NA) with various illumination settings to generate imaging to support the 65nm node technology generation.
The challenge is developing imaging solutions for 180 nm trench lithography that provides maximum overlapping process windows for imaging through pitch. The issue has been addressed first; through simulation to optimize illumination, secondly; with experimentation and the collection of data through dose and focus for a number of pitch sequences with several illumination conditions for each CD. Our problem is how to handle the comparison of many ED windows and still be able to determine which set of conditions provide the best result, the POP factor (Pitch Optimization Process) was determined. The authors will review the POP factor to demonstrate a possible new technique in the calculation of multiple pitch ED windows.
Stephen Hsu, Xuelong Shi, Chungwei Michael Hsu, Noel Corcoran, J. Fung Chen, Sunil Desai, Micheal Sherrill, Y. Tseng, H. Chang, J. Kao, Alex Tseng, WeiJyh Liu, Anseime Chen, Arthur Lin, Jan Kujten, Eric Jacobs, Arjan Verhappen
For cost effective 130nm node manufacturing, it is prefer to use KrF binary chrome mask. To realize a production worth process for making random logic device, we need to effectively control mask error enhancement factor (MEEF) through pitch. In low k1 lithography, process parameters such as focus, lens aberration, linewidth, and line pitch, style of proximity correction (OPC), and resist process conditions, etc., all impact MEEF. We show a powerful RuMBa OPC method that can reduce MEEF to an acceptable level (close to 1(using KrF resist process. We believe that RuMBa OPC method can be further extended for sub 100nm ArF process. In wafer printing experiment, we have designed a new style of LineSweeper reticles for our lithography process optimization. Both simulated and printed wafer CD data were used to calculate the overlapped process window along with respective MEEF. These are the metric we used to assess the 130nm process performance. Using RuMBa OPC, we are able to achieve overlapped process window that is sufficient for 130nm gate mask process. The CD through pitch calibration is critical for an accurate model-based correct at location where OPC rule cannot cover. A high accuracy CD through pitch calibration methodology is developed for model calibration. In this paper, we have compared the 130nm performance using KrF binary mask, KrF 6% attenuated PSM, and ArF binary mask.
Stephen Hsu, Xuelong Shi, Robert Socha, J. Fung Chen, Jason Yee, Mohan Anath, Sunil Desai, Philip Imamura, Micheal Sherrill, Y. Tseng, H. Chang, J. Kao, Alex Tseng, WeiJyh Liu, Anseime Chen, Arthur Lin, Jan Kujten, Eric Jacobs, Arjan Verhappen
This paper describes the design and implementation of a system for monitoring the performance of several major subsystems of a critical dimension measurement scanning electron microscope (CD-SEM). Experiments were performed for tests involving diagnosis of the vacuum system and column stability by monitoring of the following subsystems and associated functional parameters. These include: 1) Vacuum system with pressure as a function of time being recorded for the electron-optical column (gun chamber), the specimen chamber, and the sample-loading unit. 2) The action of several components of the wafer handling system can be timed. 3) The electron gun emission currents and other signals to monitor the characteristics of the condenser and objective lenses may be used to correlate with image quality. 4) Image sharpness, electron beam current, signal-to-noise ratio, etc. can be evaluated.
Step and Scan technology has matured for the current generation of semiconductor lithography tools and has become the standard for most new fabs and fab expansions. It is estimated that for the year 1999, more than 64 percent of new exposure tool shipments from all vendors were step and scan platforms. For economical mass production in sub 180 nm applications, DUV and i-line lithography have to be combined with critical layers that are exposure during DUV. Semi- critical and non-critical layers are exposed using i-line. The choice to use a stepper ora scanner for the i-line platform becomes critical in terms of operating cost and technical capability. This paper reports on the performance of high resolution, high throughput i-line scanners that are used in mix and match with DUV scanners. Advanced imaging capability is demonstrated on the ASML PAS 5500/400 i-line scanner as well as alignment performance on the most difficult layers using the ATHENA advanced alignment system. Matching strategies are presented along with a cost analysis showing the merits of using i-line scanners for semi- critical and non-critical layers in mix and match.
The trend in the semiconductor industry is towards superior imaging performance requiring fundamentally tighter control of device Critical Dimensions (CD) and yield. This paper focuses on the analysis of reticle contributions to intrafield CD Uniformity for step and repeat 0.25 micrometer DUV Lithography. A method is described to subtract the reticle fingerprint contribution from the CD measurement data. The method demonstrated that CD Uniformity, in terms of 3(sigma) , is perhaps only a valid statically allowed estimate if it is used after reticle correction. The extensive intrafield CD uniformity evaluation was performed on a typical ASML PAS 5500/300 DUV stepper to determine the impact of various illumination conditions. For APEX-E2408 photoresist, the actual intrafield CD uniformity was 13 nm (3(sigma) ) at best focus and 14 nm (3(sigma) ) over a 0.6 micrometer focus range for 0.25 micrometer dense lines and annular illumination with a NA equals 0.54. Subtracting the reticle fingerprint yields the exposure tool CD component of 8 nm (3(sigma) ) at best focus and 8 nm (3(sigma) ) over a 0.6 micrometer focus range. This is smaller than the reticle CD error component of 10 nm (3(sigma) ) which results from 32 nm (3(sigma) ) mask CD uniformity and a reticle sensitivity factor of 1.3. It is, therefore, imperative to reduce the reticle CD influence to realize further resolution reductions in manufacturing. Subtracting the reticle CD non-uniformity contribution allows us more accurately to determine the lithographic tool contribution to the CD uniformity budget.
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