Today’s CD-SEM metrology is challenged when it comes to measuring complex features found in patterning hotspots (like tip to tip, tip to side, necking and bridging). Metrology analysis tools allow us to extract SEM contours of a feature and convert them into a GDS format from which dimensional data can be extracted. While the CD-SEM is being used to take images, the actual measurement and the choice of what needs to be measured is done offline. Most of the time this method is used for OPC model creation but barely for process variability analysis at nominal process conditions. We showed in a previous paper  that it is possible to study lithography to etch transfer behavior of a hotspot using SEM contours. The goal of the current paper is to go extend this methodology to quantify process variability of 2D features using a new tooling to measure contour data.
The concept of the multi-source focus correlation method was presented in 2015 [1, 2]. A more accurate understanding of real on-product focus can be obtained by gathering information from different sectors: design, scanner short loop monitoring, scanner leveling, on-product focus and topography.<p> </p>This work will show that chip topography can be predicted from reticle density and perimeter density data, including experimental proof. Different pixel sizes are used to perform the correlation in-line with the minimum resolution, correlation length of CMP effects and the spot size of the scanner level sensor. Potential applications of the topography determination will be evaluated, including optimizing scanner leveling by ignoring non-critical parts of the field, and without the need for time-consuming offline topography measurements.
The desire to reduce cost in volume manufacturing has driven up the throughput in the lithographic exposure machines.
As a result the power transmitted in the projection optics increases. Although small, the absorption levels in the lens
materials are not zero, which leads to localized heating of the lens and hence lens aberrations. To squeeze out the
maximum process windows, the pupil shapes have transformed from simple annular shapes to shapes with very
concentrated poles. As a result, the exposure energy transported through the lens is no longer equally distributed over the
lenses of the projection options. Instead only a fraction of the lens gets to transport the total power. This concentration of
power further aggravates the lens heating induced aberrations and enhances the importance of advanced lens heating
control schemes which are available on ASML scanners.
To analyze the effects of lens heating on the final imaging, a model was developed by the lens manufacturer Carl Zeiss
SMT GmbH, and incorporated into a litho simulation environment by ASML BRION. This tool can be used to analyze
the impact of dose/throughput, illumination shapes and reticle layout on aberrations. It provides a means to assess
potential lens heating issues even before production masks are manufactured. Moreover, this computational tool opens
the possibility to calculate parameters for lens heating correction, rather than measuring them, saving valuable machine
time. In this paper, the performance of the novel computational lens heating control is demonstrated on wafer and
compared with the traditional way of measuring the relevant parameters. In addition, a modeling study is performed to
assess possible lens heating effects for freeform or non-traditional source shapes, thereby demonstrating the advanced
correction potential of ASML latest aberration manipulator, called FlexWave<sup>TM</sup>.
Once a process is set-up in an integrated circuit (IC) manufacturer's fabrication environment, any drift in the proximity
fingerprint of the cluster will negatively impact the yield. In complement to the dose, focus and overlay control of the
cluster, it is therefore also of ever growing importance to monitor and maintain the proximity stability (or CD through
pitch behavior) of each cluster.
In this paper, we report on an experimental proximity stability study of an ASML XT:1900i cluster for a 32 nm poly
process from four different angles. First, we demonstrate the proximity stability over time by weekly wafer exposure and
CD through pitch measurements. Second, we investigate proximity stability from tool-to-tool. In a third approach, the
stability over the exposure field (intra-field through-pitch CD uniformity) is investigated. Finally, we verify that
proximity is maintained through the lot when applying lens heating correction.
Monitoring and maintaining the scanner's optical proximity through time, through the lot, over the field, and from toolto-
tool, involves extensive CD metrology through pitch. In this work, we demonstrate that fast and precise CD through
pitch data acquisition can be obtained by scatterometry (ASML YieldStar<sup>TM</sup> S-100), which significantly reduces the
The results of this study not only demonstrate the excellent optical proximity stability on a XT:1900i exposure cluster for
a 32 nm poly process, but also show how scatterometry enables thorough optical proximity control in a fabrication
If the minimum die area is the main objective of an ASIC application, then each critical layer will have bi-directional
mask layout. Then advanced litho technology is required to print the layers with single exposure lithography. If however
yield, electrical robustness and variability have higher priority than minimum die area, than unidirectional patterning can
be a good alternative. However, then the bi-directional layout of, especially the active area- and gate-layer, must be
redesigned in an unidirectional layout (at the expense of a larger cell-area). Moreover, if a design split in two orthogonal
unidirectional layouts can be made then the so-called cut-mask technology can be used: this is a (well-known) double
patterning technology. This paper discusses three different cut-mask compatible redesigns of the gate-layer of a complex
flip-flop cell, to be used in robust, low-cost low-power CMOS-logic applications with 45 nm ground rules and 180 nm
device pitches. The analogue circuit simulator from Cadence has been used. The results obtained with ASML's
lithography simulator, "Litho Cruiser", show that cut-mask patterning gives superior CD- and end-of-line control and
enables Design Rules with less Gate-Overlap. This again gives the circuit-designer more design freedom for choosing
the transistor width. Furthermore, the cut-mask compatible layouts can even be processed with high-NA dry KrFlithography
instead of advanced single exposure ArFi lithography. The designs are compared with a reference design
which is a traditional minimum area design with bi-directional layout.
The lithography prognosticator of the early 1980's declared the end of optics for sub-0.5&mgr;m imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k<sub>1</sub>. Several author have recently discussed manufacturing imaging solutions for sub-0.3k<sub>1</sub> and the integration challenges.
Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k<sub>1</sub> imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.
C045 node (65nm half pitch) technology processes are driving the development of immersion lithography techniques and infrastructures and C032 node (45nm half pitch) is following in its tracks. As semiconductor development enters the arena of low leakage, high-performance devices using immersion lithography, the 45nm hp technology adds more pressure of decreasing pitches and feature sizes using the most cost effective method available. The Crolles2 Alliance is in the first phases of the push for very low k1 193nm lithography for our technology development. Many resolution enhancement techniques are being explored to fill the low k1 realm; including implementation of these techniques and more aggressive integrations to support the device parameters.
However, the early development of 45nm hp node along with the need for better focus and dose control algorithms, imaging of pitches to allow for the packing density will present significant challenges to photolithography even when considering super hyper-NA immersion lithography. Reflectivity variations, thin film interference through the complex film stacks, and increased sensitivity to feature size is posing a challenge for maintaining good and consistent features.
This paper discusses an analysis and early results covering the beginning development of 45nm hp with >1NA immersion lithography. Specifically, parameters such as illumination and enhancement techniques, processing capability, application of OPC at a very low k1, process integration, mask effects, and defectivity as discussed.
Semiconductor manufacturers work hard to shrink critical dimensions in their device architectures and are in the midst of the 45nm node development. Generally, for the 65nm node, critical layers are processed using 193-nm scanners with numerical apertures up to 0.85 and non-immersion technology. It is clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) need to be examined, especially as the industry turns its attention towards the 45-nm technology generation. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported.
In this paper, we report on the progress of development for the 45nm device level lithography with imaging systems >1NA at the Crolles 2 Alliance. Our continued focus is the insertion of an immersion lithography process into an established pilot manufacturing line to support 45nm process development. We will present immersion resist performance, OPC feasibility, process integration, and defectivity comparisons. Finally, conclusions will be made as to the overall readiness of immersion to support 45nm node processing.
Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (<i>hp</i>90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (<i>hp</i>65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).
On-going complex integration schemes and developments in processes present significant challenges to lithography in manufacturing advanced semiconductor integrated circuits. Although APC solutions are in place to assist in achieving robust CD control and overlay, there is a great need to increase the 'knowledge' of the system with respect to other contributors impacting the process. The problem becomes more complex in case of an ASIC Prototyping Fab where there is no big runner concept. This leads to the need of a product effect management requirement (Product layout and reticles impact). For this reason, we developed the multivariate R2R controller. This paper discusses the multi-variant methodology and results of a new R2R regulation algorithm in a 65nm node process. Specifically, parameters such as linear combinations of terms, alignment variation for overlay modeled parameters (inter-field / intra-field), CD impacts (reticles, process, tool, STI stack etc) are studied. New solutions for future technology nodes are presented in this paper. It includes for each contributor a multivariate method to assess vector responses and noise contribution. This is being applied on CD and Overlay measurement feedback. For each source of variation (or "Contributor"), the multivariate controller provides the estimated level of compensation requested to meet the target and the level of noise induced on lot processing. At the moment the multivariate R2R controller runs in production. A real evaluation of the existing sources of variations and noise is possible and demonstrated. The result is a significant regulation performance improvement.