Over the past few years, we have spent quite some effort to demonstrate that the off-line mask-to-mask overlay as determined on the PROVE tool correlates very well with the on-wafer overlay as measured by the scanner. The role and placement of the reticle alignment marks was considered in this analysis together with the reticle alignment model. The excellent correlation (R2 < 0.96) could only be achieved by a carefully set-up experiment. All potentially disturbing additional overlay contributors were ruled out. By doing so, a one-to-one comparison between the off-line determined mask-to-mask overlay and the on-wafer measured overlay could be made. This means that the mask-to-mask overlay as measured by PROVE directly translates into an on-product overlay contribution. The residual mismatch of ~ 0.6-nm could be attributed to the scanner itself and the sampling difference between a PROVE measurement and that of the alignment sensor inside the scanner. In this follow-up work, we will make a start to apply the knowledge that was obtained previously to a use-case that is much closer to what is common practice in the industry. An N7 equivalent technology process has been selected in combination with a state-of-the-art mask. This mask was made on an EBM-9000 system and contains μ-DBO (Diffraction Based Overlay) targets that can be readout on an ASML Yieldstar (YS:375) overlay metrology tool. Moreover, the mask contains electrical-test structures and random logic features. This makes it possible to study the onproduct overlay performance from the exposure field level down to a single logic feature on the mask! The mask is not the only contributor to the on-product overlay. Other on-product overlay contributors may be present as well. The current investigation aims to understand the on-product overlay performance by identifying the underlying contributors. This is done by considering the overlay as measured on the μ-DBO targets. The mask writing, etch, scanner, and metrology contributions are being addressed. We show that the mask contribution as part of the on-product overlay budget is comparable with the overlay performance of the state-of-the-art scanner ASML NXT:2000i (≤ 1.4-nm single machine overlay, dedicated chuck, full wafer coverage) that was used in this work. The goal of this paper is to set and understand the baseline for the intra-field on-product overlay performance as measured on YS overlay targets including all its sub-contributors. This enables us to make the next step towards local placement errors for individual device structures.
The etch induced on-product overlay performance across wafer has received quite some attention recently. Global wafer overlay penalties have been observed by realizing that the etch direction is not always perpendicular to the wafer surface and may vary slightly as a function of the wafer radius due to the geometry and plasma parameter settings of the etch tool. In particular close to the wafer edge, for radii in between 130-mm and 150-mm, the etch direction may change even more strongly and is not constant over time. This is due to a consumable part inside the etch tool, the so-called focus ring. Control solutions based on optical overlay metrology have been developed and have found their way into tunable focus rings. The general concept is to keep the etch direction perpendicular to the wafer surface throughout the life-time of the focus ring. The general belief is that these global etch induced overlay penalties can be mitigated by applying these newly developed hardware control solutions. In this experimental work, we go one level deeper and consider the more local etch induced overlay penalties. This time etch effects on length scales on the order of exposure field and/or die level are addressed. The intra-field etch induced overlay penalties are characterized by considering the overlay measurement after resist development (ADI) and after etch (AEI). Surprisingly, the observed penalties are on the order of ~1-nm within each individual exposure field despite the fact that away from the wafer edge the etch direction is considered to be close to perpendicular to the wafer surface. In this experimental work, etch tool parameters like low frequency (LF) power and pressure have been varied to reveal the nature of these die-level overlay penalties. Based on the experimental results, we present a hypothesis of the underlying mechanism that explains the etch induced intra-field overlay penalties and provide solution directions to mitigate these kinds of overlay penalties.
It has been demonstrated that the mask-to-mask overlay contribution can be fully characterized by off-line measurements on the PROVE mask registration tool. This characterization includes the impact of the marks that are used for reticle alignment inside the scanner. This is an important aspect since the scanner is blind to the features inside the image field and intra-field adjustments are only based on measurements of the reticle alignment marks. The off-line determined mask-to-mask overlay was compared with the measured on-wafer results and a perfect correlation (R2 < 0.96) was found. The residual mismatch was around 0.6-nm, which is 30% of the dedicated chuck overlay performance of the scanner that was used. These results enable feed-forward corrections to the scanner to improve the intra-field overlay performance or to predict the intra-field overlay originating from mask writing errors (computational overlay). We recently extended the work to the layer-to-layer overlay impact by considering the mask writing error of a wafer alignment mark. This wafer alignment mark was exposed in the first layer. Apart from the reticle writing error of the wafer alignment mark itself, the reticle alignment contribution performed on dedicated reticle alignment marks inside the scanner plays an important role as well. The actual position of the selected wafer alignment mark is also impacted by the reticle alignment model corrections at that specific field location. Only when both contributors are considered, the layer-to-layer overlay can be predicted accurately. In this scenario, the layer-to-layer overlay is measured back to the layer in which the alignment marks were defined. This is referred to as the direct alignment use-case. In this paper, we further investigate the direct alignment use-case in relation to the layer-to-layer overlay. Apart from the reticle writing error and the reticle alignment corrections, the actual placement of the wafer alignment mark during exposure can also be affected by other applied corrections. We will present experimental results of the layer-to-layer overlay as function of the applied automated process corrections on the wafer alignment mark location printed in the first layer. It is shown that the wafer alignment sensor impact should be considered as well in the interpretation of the results. We finally present a strategy to control these kinds of overlay errors.
The mask-to-mask writing error contribution as part of the on-wafer intra-field overlay performance has been extensively studied over the past few years. An excellent correlation (R2 > 0.96) was found between the off-line registration measurements by the PROVE tool and the on-wafer intra-field overlay results. The residual mismatch between the offline registration measurements and the on-wafer intra-field overlay was around 0.58-nm. This value is approximately 30% of the dedicated chuck overlay performance of the scanner that was used. A careful analysis was performed to understand and quantify the two dominant underlying contributors that are responsible for the 0.58-nm mismatch. The first contributor could be attributed to the reproducibility of the reticle alignment of the scanner (~0.43-nm after 10 wafers averaging). The second contributor was assigned to the sampling difference between the PROVE registration measurement and that of the alignment sensor inside the scanner (~0.39-nm). The sampling difference is a direct result of the relatively large metrology feature (alignment mark diffraction grating) in combination with older generation e-beam mask writing tools that were used in the experiments. Local grating placement variations are averaged out when the scanner alignment sensor is used for an overlay measurement. This is due to the large spot size and the scanning principle to obtain a position. This is fundamentally different for a mask registration tool since it has been designed to perform dedicated measurements on single features (globally or in-die) across the entire mask. Previous investigations used only two sampling points for each individual alignment mark diffraction grating in order to keep the total number of measurements and time under control. It is expected that the sampling difference will significantly decrease if state-of-the-art mask e-beam writers are used and/or if the number of sampling points as measured by the PROVE will be increased. It might be obvious that the ability to perform dense off-line local registration measurements has large value to reveal local mask writing errors. The new local registration map (LRM) mode of PROVE can be used to average out local reticle writing errors enabling a more accurate placement determination of large metrology features like reticle and/or wafer alignment marks. The application of LRM can be used to further improve the accuracy between the scanner and the PROVE mask registration tool if required. So far, all published correlation studies between off-line mask registration measurements and on-wafer overlay measurements were based on TIS (Transmission Image Sensor) reticle alignment marks. In this paper, we have applied LRM to improve the placement accuracy of more advanced PARIS (Parallel ILIAS) reticle alignment marks. A comparison with on-wafer measurements is made. In addition, the placement accuracy of a wafer alignment mark is considered as well. The impact of a wafer alignment mark placement error due to reticle writing errors on the intra-field overlay is experimentally determined and discussed. This includes the effect of an applied intra-field scanner (reticle alignment) correction on the wafer alignment mark placement.
One of the contributors to layer-to-layer overlay in today’s chip manufacturing process is wafer distortion due to thin film deposition. Mismatch in the film specific material parameters (e.g., thermal expansion coefficients) may result in process-induced warpage of the wafers at room temperature. When these warped wafers are loaded onto the scanner for the next layer exposure, in-plane distortion patterns may be apparent after clamping. The wafer alignment system inside the scanner is designed to correct for these process-induced in-plane wafer distortion signatures. Depending on the complexity of the distortion pattern, the choice of wafer alignment model can be adapted to achieve the required overlay performance. While wafer overlay metrology is used to correct for the systematic part of the wafer distortion, the wafer alignment functionality addresses the random part that is varying from wafer-to-wafer.
In the case of a homogeneous single film of uniform stress deposited on a substrate at elevated temperatures inside a deposition tool, the resulting free-form wafer shape at room temperature will take a parabolic form (either bowl or umbrella). The resulting in-plane distortion can be described by a radial scaling pattern. A linear wafer alignment model can easily correct for these kinds of distortion patterns and the resulting overlay is close to the scanner baseline performance. Also, in the case where there is a slight variation in one of the material parameters across the wafer, the resulting wafer distortion can easily be corrected for by selecting one of the available wafer alignment models. A Higher Order Wafer Alignment model up to the third order (HOWA3) has been proven to be sufficient to bring the overlay performance down to the scanner baseline performance over the past years.
In this paper we will consider the impact of local stress variations on the global wafer deformation. One of the sources of the local stress variation is linked to the intra-field or intra-die pattern density. We will demonstrate that the intra-field stress distribution not only affects the intra-field overlay performance but has also a significant impact on the global wafer distortion. The focus will be mainly on use-cases with high intra-field stress variations similar to what is encountered in 3D-NAND processes. These cases in particular need a more advanced correction approach. However, since the underlying root cause is generic, the same approach may also be applicable to other use-cases like DRAM and Logic.
Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region.
In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements.
Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.
Three methods to minimize the impact of alignment mark asymmetry on overlay variation are demonstrated. These methods are measurement based optimal color weighting (OCW), simulation based optimal color weighting, and wafer alignment model mapping (WAMM). Combination of WAMM and OCW methods delivers the highest reduction in overlay variation of 1.3nm (X direction) and 1.2nm (Y direction) as compared to best single color recipe. Simulation based OCW produces a similar reduction in overlay variation as compared to measurement based OCW, and simulation based OCW has the advantage that the scanner alignment recipe with optimize weights can be determined before the mark asymmetry excursion has occurred. Finally, WAMM is capable of reducing the contribution of mark asymmetry on overlay by using a more optimal high order wafer alignment recipe. Capabilities of WAMM can also be combined with OCW solutions.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.
Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.
The defectivity challenges of extreme ultraviolet (EUV) masks, that need to be addressed before production readiness of EUV lithography is assured from the mask perspective, are twofold. First, the EUV-specific defect type relating to the multi-layer (ML) mirror, the so-called ML-defects, require to become more detectable than they are printable. This not only requires proven capability of blank inspection, but also the existence of satisfactory printability mitigation strategies (comprising avoidance, pattern shift methodology, compensation repair). Both these assets need to become available within the mask supply chain, as there is little that can still be done about such residual defects at the wafer fab. In a production phase, finding unexpected printing ML-defects is unacceptable. It is shown how the specific way-of-working in use at imec, starting from the printed wafer, contributes to related learning and identification of remaining gaps, in getting this issue fully dealt with. The second challenge relates to particle contamination during use of the reticle at the wafer fab. Avoiding overlaycritical particles on the backside of NXE3100 reticles is facilitated by the established way-of-working. Minimizing the occurrence of particles “hopping” between reticles via the electrostatic clamp of the scanner (so-called clamp-traveling particles) is a major driver for appropriate mask cleaning. The latter may not have negative impact by frequent use, in view of the highly vulnerable EUV mask stack, and especially for the present “black-border” solution in which the ML is etched away at the image border on the reticle. A lot of effort is spent into monitoring of NXE3100 reticles for particle adders on the pattern side. This is realized by comparing past and present mask defect maps obtained by inspection of printed wafers with subsequent repeater analysis.
For the 14nm node and beyond there are many integration strategy decisions that need to be made. All of these can have a significant impact on both alignment and overlay capability and need to be carefully considered from this perspective. One example of this is whether a Litho Etch Litho Etch (LELE) or a Self Aligned Double Patterning (SADP) process is chosen. The latter significantly impacting alignment and overlay mark design. In this work we look at overlay performance for a Back End of Line (BEOL) SADP Dual Damascene (DD) process for the 14nm node. We discuss alignment mark design, particularly focusing on the added complexity and issues involved in using such a process, for example design of the marks in the Metal Core and Keep layers and recommend an alignment scheme for such an integration strategy.
To make sure a baseline process will be ready for the evaluation of the NXE:3300, imec evaluates promising new EUV resist materials with regards to imaging, process window and line width roughness (LWR) performance. From those screening evaluations, highest performing materials meeting dose sensitivity requirements are selected to be installed on the coat/develop track. This work details the process optimization results of the different selected resist platforms with regards to full wafer processing. Evaluations are executed on the ASML NXE:3100 equipped with a laser-assisted discharge produced plasma source from XTREME technologies, and interfaced to a TEL CLEAN TRACKTM LITHIUS ProTM -EUV.
For device manufacturing at the 10nm node (N10) and below, EUV lithography is one of the technology options to
achieve the required resolution. Besides high throughput and extreme resolution, excellent wafer CD, overlay and defect control are also required. In this paper, we discuss two wafer CD uniformity issues, the effect of the reticle black border and photon shot noise. The readiness of EUV lithography for N10 will be discussed by showing on-product imaging and overlay performance of a self aligned via layer inserted with EUV lithography. EUV single patterning results will be discussed by comparing the imaging performance of our NXE:3100 cluster to the NXE:3300 at ASML. Last but not least, the extendibility of EUV lithography towards sub 10nm patterning will be discussed by demonstrating sub 10nm half pitch LS patterns with EUV single Self Aligned Double Patterning (SADP).
Previously, fundamental evaluations of the Extreme Ultra Violet (EUV) lithography process have been conducted using
the CLEAN TRACK ACT™ 12 coater/developer with the ASML EUV Alpha Demo Tool (ADT) at imec. In that
work, we confirmed the basic process sensitivities for the critical dimension (CD) and defectivity with EUV resists.
Ultimate resolution improvements were examined with TBAH and FIRM™ Extreme. Moving forward with this work,
the latest inline cluster is evaluated using the ASML NXE:3100 pre-production EUV scanner and the CLEAN
TRACK™ LITHIUS Pro™ -EUV coater/developer. The imec standard EUV baseline process has been evaluated for
manufacturability of CD uniformity control based on half pitch (HP) 27nm and ultimate resolution studies focusing on
HP 22nm. With regards to the progress of the improvement for EUV processing, we confirmed the effectiveness of
several novel concepts: FIRM™ Extreme10 showed increase in ultimate resolution and improvement in line width
roughness (LWR) and process window; Tokyo Electron LTD. (TEL) smoothing process for roughness reduction showed
17% improvement for line and space (L/S) patterns; and finally the new dispense method reduced patterned wafer
defectivity by over 50%.
EUV lithography is a candidate for device manufacturing for the 16nm node and beyond. To prepare for insertion into
manufacturing, the challenges of this new technology need to be addressed. Therefore, the ASML NXE:3100 preproduction
tool was installed at imec replacing the ASML EUV Alpha Demo Tool (ADT). Since the technology has
moved to a pre-production phase, EUV technology has to mature and it needs to meet the strong requirements of sub
16nm devices. We discuss the CD uniformity and overlay performance of the NXE:3100. We focus on EUV specific
contributions to CD and overlay control, that were identified in earlier work on the ADT. The contributions to overlay
originate from the use of vacuum technology and reflective optics inside the scanner, which are needed for EUV light
transmission and throughput. Because the optical column is in vacuum, both wafer and reticle are held by electrostatic
chucks instead of vacuum chucks and this can affect overlay. Because the reticle is reflective, any reticle (clamp)
unflatness directly translates into a distortion error on wafer (non-telecentricity). For overlay, the wafer clamping
performance is not only determined by the exposure chuck, but also by the wafer type that is used. We will show wafer
clamping repeatability with different wafer types and discuss the thermal stability of the wafer during exposure.
In state of the art production, in order to obtain the best possible overlay performance between critical layers, wafers are
often dedicated to one scanner and all layers processed on that scanner, and in the case of scanners with dual stages, this
often extends to stage dedication as well. Meeting the overlay performance requirements becomes even more complex
with the introduction of EUV lithography into production. It will not be possible to expose all critical layers on an EUV
scanner, which will only be used for some of the most critical layers, the other critical layers will remain on 193nm
immersion scanners. It therefore needs to be demonstrated that the same overlay performance is achievable when tool
types are mixed and matched as when we run with tool dedication. To do this it is critical that we understand the overlay
matching characteristics of 193nm immersion and EUV scanners and from this learn how to control them, so that the
optimum strategy can be developed and overlay errors between these tool types minimized.
In this work we look at the matching performance between two generations of 193nm immersion scanner and an EUV
pre-production tool. We evaluate the matching in both directions, first layer on immersion, second layer on EUV and
vice-versa, and demonstrate how optimum matching can be achieved, so that insertion of an EUV scanner into
production for the required imaging does not result in a degraded overlay capability. We discuss the difference in grid
and intrafield signatures between the tool types and how this knowledge can be used to minimize the overlay errors
between them and if there are any new concerns which impact the chosen strategy when the two tool types are mixed
Extreme Ultra-Violet (EUV) lithography is a candidate for semiconductor manufacturing for the 16nm technology node
and beyond. Due to the very short wavelength of 13.5nm, EUV lithography provides the capability to continue single
exposure scaling with improved resolution and higher pattern fidelity compared to 193nm immersion lithography.
However, reducing the wavelength brings new equipment and process challenges. To enable EUV photon transmission
through the optical system, the entire optical path of an EUV exposure tool operates under vacuum, and in addition
reticle and optics are reflective. To obtain the required CD and overlay performance, both wafer and reticle front surfaces
need to have near-perfect flatness, as non-flatness directly contributes to focus and image placement errors, in the case of
the reticle due to non-telecentricity. Traditional vacuum chucks, both for reticle and wafer, cannot be used and are
replaced by electrostatic chucks. Any contribution of this new clamping method on CD and overlay control therefore
needs to be investigated, including avoidance of particle contamination over time. This work was performed on ASML's
EUV Alpha Demo Tool (ADT). We investigated the different, non-conventional contributions to overlay control on the
ADT, with particular attention to the wafer clamping performance of the exposure chuck. We demonstrate that we were
able to improve the overlay performance by compensating for the wafer clamping error during the wafer alignment
sequence. The impact of different wafer types on overlay was also evaluated. In addition to clamping effects, thermal
effects have also been shown to impact overlay and were evaluated by monitoring the thermal behavior of a wafer during
exposure on the ADT and correlating to the resulting overlay.
In order to further understand the processing sensitivities of the EUV resist process, TEL and imec have continued their
collaborative efforts. For this work, TEL has delivered and installed the state of the art, CLEAN TRACK™ LITHIUS
Pro™ -EUV coater/developer to the newly expanded imec 300mm cleanroom in Leuven, Belgium. The exposures
detailed in this investigation were performed off-line to the ASML EUV Alpha Demo Tool (ADT) as well as on the inline
ADT cluster with CLEAN TRACK™ ACT™ 12 coater/developer. As EUV feature sizes are reduced, is it apparent
that there is a need for more precise processing control, as can be demonstrated in the LITHIUS Pro™ -EUV. In
previous work from this collaboration1, initial investigations from the ACT™ 12 work showed reasonable results;
however, certainly hardware and processing improvements are necessary for manufacturing quality processing
performance. This work continues the investigation into CDU and defectivity performance, as well as improvements to
the process with novel techniques such as advanced defect reduction (ADR), pattern collapse mitigation with FIRM™Extreme and resolution improvement with tetrabutylammoniumhydroxide (TBAH).
In many ways, sidewall spacer double patterning has created a new paradigm for lithographic roadmaps. Instead of
using lithography as the principal process for generating device features, the role of lithography becomes to generate a
mandrel (a pre-pattern) off-of-which one will subsequently replicate patterns with various degrees of density
multiplication. Under this new paradigm, the innovativeness of various density multiplication techniques is as critical to
the scaling roadmap as the exposure tools themselves.
Sidewall spacer double patterning was the first incarnation of mandrel based patterning; adopted quickly in NAND flash
where layouts were simple and design space was focused. But today, the use of advanced automated decomposition
tools are showing spacer based patterning solutions for very complex logic designs. Future incarnations can involve the
use of laminated spacers to create quadruple patterning or by retaining the original mandrel as a method to obtain triple
patterning. Directed self-assembly is yet another emerging embodiment of mandrel based patterning, where selfseparating
polymers are registered and guided by the physical constraint of a mandrel or by chemical pre-pattern trails
formed onto the substrate.
In this summary of several bodies of work, we will review several wafer level demonstrations, all of which use various
forms of mandrel or stencil based density multiplication including sidewall spacer based double, triple and quadruple
patterning techniques for lines, SADP for via multiplication, and some directed self-assembly results all capable of
addressing 15nm technology node requirements and below. To address concerns surrounding spacer double patterning
design restrictions, we show collaboration results with an EDA partner to demonstrate SADP capability for BEOL
routing layers. To show the ultimate realization of SADP, we partner with IMEC on multiple demonstrations of
As Extreme ultraviolet (EUV) lithography technology shows promising results below 40nm feature sizes, TOKYO
ELECTRON LTD.(TEL) is committed to understanding the fundamentals needed to improve our technology, thereby
enabling customers to meet roadmap expectations. TEL continues collaboration with imec for evaluation of
Coater/Developer processing sensitivities using the ASML Alpha Demo Tool for EUV exposures. The results from the
collaboration help develop the necessary hardware for EUV Coater/Developer processing. In previous work, processing
sensitivities of the resist materials were investigated to determine the impact on critical dimension (CD) uniformity and
defectivity. In this work, new promising resist materials have been studied and more information pertaining to EUV
exposures was obtained. Specifically, post exposure bake (PEB) impact to CD is studied in addition to dissolution
characteristics and resist material hydrophobicity. Additionally, initial results show the current status of CDU and
defectivity with the ADT/CLEAN TRACK ACTTM 12 lithocluster. Analysis of a five wafer batch of CDU wafers shows
within wafer and wafer to wafer contribution from track processing. A pareto of a patterned wafer defectivity test gives
initial insight into the process defects with the current processing conditions. From analysis of these data, it's shown that
while improvements in processing are certainly possible, the initial results indicate a manufacturable process for EUV.
The 22nm technology node is the target for insertion of Extreme Ultra-Violet (EUV) lithography into pre-production. To
prepare this insertion, the issues that arise with the use of an EUV lithographic scanner in a pre-production environment
need to be addressed. To gain better understanding of the issues that come with an EUV lithographic scanner, the Alpha
Demo Tool (ADT) from ASML was installed at IMEC and is now in use since mid of 2008. In July 2009, the source was
upgraded to a 170W/2π source to allow for higher uptime and wafer output by means of the semi-automatic tin refill.
Also a new advanced resist, the SEVR-59 resist was introduced after the installation of the 170W/2π source to allow
printing of 32nm Lines-Spaces (LS). After these changes, the ADT has been monitored closely with respect to the
imaging performance. In this paper, we report on both the CD fingerprint analysis and the exposure tool stability. For
32nm dense LS, the ADT shows a wafer CD Uniformity (CDU) of 2.5nm 3σ, without any corrections for process or
reticle. As for 40nm LS, the wafer CDU is correlated to different factors that are known to influence the CD fingerprint
from traditional lithography: reticle CD error, slit intensity uniformity, focal plane deviation but also EUV specific
reticle shadowing. The ADT shows excellent wafer-to-wafer stability (<0.5nm CD range in a 5-wafer lot) and the
average CD as a function of exposure sequence is stable (<0.5nm 3σ in a 5-wafer lot). The ADT shows good CD
stability over 5 months of operation with the 170W/2π source, both intrafield and across wafer. There is a 5nm difference
in overlay performance (measured or after corrections) between the ADT and the XT:1900Gi production tool (using the
same etched silicon wafers as a reference). Below 32nm, the ADT shows good wafer CDU for 30nm dense LS (60nm pitch). First 27nm dense line CDU data are achieved (54nm pitch). The results indicate that the ADT can be used effectively for EUV process development before installation of the pre-production tool, the ASML NXE:3100 at IMEC.
As lithographic technology is moving from single pattern immersion processing for 45nm node to double patterning for
the next generation and onward to EUV processing, TEL is committed to understanding the fundamentals and improving
our technology to enable customers to meet roadmap expectations. With regards to immersion and double patterning
technology, TEL has presented a wide variety of technologies to advance the processing capability of our customers.
With regards to EUV technology, we have previously presented work for simulation and modeling of an EUV resist
system1 in order to further our understanding of the differences between resist performance from previous platforms and
currently available EUV resists. As it's currently unknown which direction resist suppliers will take with regards to
platform in order to surpass the current limitations in resolution, roughness and sensitivity trade off's, we need to
consider the implications of such kinds of novel platforms to track processing capabilities. In this work, we evaluated
two of the more promising materials, to determine processing sensitivities necessary for the development of new
hardware and process applications. This paper details the initial study complete for understanding the track process
parameters such as dissolution characteristics and the impact of film hydrophobicity. Fundamental processing
knowledge from 193 and 248nm technology is applied to understand where processing deviates from known sensitivities
and will require more development efforts.
EUV blank non-flatness results in both out of plane distortion (OPD) and in-plane distortion (IPD) [3-5]. Even for extremely flat masks (~50 nm peak to valley (PV)), the overlay error is estimated to be greater than the allocation in the overlay budget. In addition, due to multilayer and other thin film induced stresses, EUV masks have severe bow (~1 um PV). Since there is no electrostatic chuck to flatten the mask during the e-beam write step, EUV masks are written in a bent state that can result in ~15 nm of overlay error. In this article we present the use of physically-based models of mask bending and non-flatness induced overlay errors, to compensate for pattern placement of EUV masks during the e-beam write step in a process we refer to as E-beam Writer based Overlay error Correction (EWOC). This work could result in less restrictive tolerances for the mask blank non-flatness specs which in turn would result in less blank defects.
Extreme Ultra-Violet (EUV) lithography is the leading candidate for semiconductor manufacturing of the 22nm
technology node and beyond, due to the very short wavelength of 13.5nm. However, reducing the wavelength adds
complexity to the lithographic process. The impact of the EUV specific conditions on lithographic performance needs to
be understood, before bringing EUV lithography into pre-production. To provide early learning on EUV, an EUV fullfield
scanner, the Alpha Demo Tool (ADT) from ASML was installed at IMEC, using a Numerical Aperture (NA) of
0.25. In this paper we report on different aspects of the ADT: the imaging and overlay performance and both short and
long-term stability. For 40nm dense Lines-Spaces (LS), the ADT shows an across field overlapping process window of
270nm Depth Of Focus (DOF) at 10% Exposure Latitude (EL) and a wafer CD Uniformity (CDU) of 3nm 3σ, without
any corrections for process or reticle. The wafer CDU is correlated to different factors that are known to influence the
CD fingerprint from traditional lithography: slit intensity uniformity, focus plane deviation and reticle CD error. Taking
these contributions into account, the CD through slit fingerprint for 40nm LS is simulated with excellent agreement to
experimental data. The ADT shows good CD stability over 9 months of operation, both intrafield and across wafer. The
projection optics reflectivity has not degraded over 9 months. Measured overlay performance with respect to a dry tool
shows |Mean|+3σ below 20nm with more correction potential by applying field-by-field corrections (|Mean|+3σ ≤10nm).
For 22nm SRAM application, both contact hole and metal layer were printed in EUV with 10% CD and 15nm overlay
control. Below 40nm, the ADT shows good wafer CDU for 30nm dense and isolated lines (on the same wafer) and 38nm
dense Contact Holes (CH). First 28nm dense line CDU data are achieved. The results indicate that the ADT can be used
effectively for EUV process development before installation of the pre-production tool, the ASML NXE Gen. 1 at
One of the main experimental setups for EUV lithography is the ASML EUV Alpha-Demo Tool (ADT), which achieves the first full-field EUV exposures at a wavelength of 13.6nm and a numerical aperture of 0.25. We report on the assessment of the baseline imaging performance of the ADT installed at IMEC, and review the work done in relation to EUV reticles and resists. For the basic imaging performance of the ADT, we have studied 40 LS patterns through dose and focus and at multiple slit positions, to extract exposure latitude and depth of focus. Measurements of reticle CD vs. wafer CD were done to determine the Mask Error Enhancement Factor (MEEF) for dense features. We also discuss the uniformity of the different features across the field, and the factors that influence it. The progress in EUV resist performance has been tracked by screening new materials on the EUV ADT. Promising resist materials have been tested on the ASML ADT and have demonstrated sub 32nm Line/Space and 34nm dense contact hole resolution. One of the main topics related to EUV reticles is reticle defectivity along with reticle defect printability. We have experimentally measured the number of wafer defects that repeat from die-to-die after reticle exposure on the ADT. To examine the wafer signature of the repeating defects, a SEM-based defect review is then conducted. We have used rigorous simulations to show that the defect signature on wafer can correspond to a relatively large ML defect, which can print as a hollow feature.
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. This paper deals with the
investigation of the impact of the mask blank architecture on the wafer print by EUV lithography. Presently the material
stack on the mask is not fixed and different suppliers offer a range of variation. The purpose of the present paper is threefold,
as detailed hereafter.
First it is shown that there are possibilities to make EUV masks less prone to reflectivity loss by carbon contamination.
An estimate is given for the required limitations on mask contamination and fabrication tolerance to keep the imaging
impact below acceptable levels. These data can be used as preliminary error budgets for the individual and combined
capping layer deterioration phenomena.
Further-on, printing results on the Alpha Demo Tool (ADT) are reported, obtained with different reticles with identical
layout produced on blanks with different mask stacks. In preparation for this experimental work simulations have been
undertaken. The experimental results show good agreement in printing performance between the reticles tested.
Finally, our work clearly shows the opportunity to reduce the absorber thickness without noticeable loss of contrast and
with the big advantage of shadowing effect reduction.
Extreme Ultraviolet Lithography (EUVL) is the leading candidate beyond 32nm half-pitch device manufacturing.
Having completed the installation of the ASML EUV full-field scanner, IMEC has a fully-integrated 300mm
EUVL process line. Our current focus is on satisfying the specifications to produce real devices in our facilities.
This paper reports on the imaging fingerprint of the EUV Alpha Demo Tool (ADT), detailing resolution, imaging,
and overlay performance. Particular emphasis is given to small pitch contact holes, which are a critical layer for
advanced manufacturing nodes and one of the most likely layers where EUVL may take over from 193nm
lithography. Imaging of contact holes, pattern transfer and successful printing of the contact hole level on a 32nm
SRAM device is demonstrated. The impact of flare and shadowing on EUV ADT performance is characterized
experimentally, enabling the implementation of appropriate mitigation strategies.
A research program on EUV lithography has been started at IMEC, based on ASMLs EUV full field scanner, the Alpha
Demo Tool (ADT). It contains three main projects: EUV resists, EUV reticles and assessment of the ADT performance.
The intent of this program is to help improve and establish the necessary mask and resist infrastructure, and achieve
learning to prepare for the use of EUV lithography in future production of integrated circuits. Good progress in resist
performance, as assessed by interference lithography, is illustrated by the ability of some materials to resolve 25nm HP.
In its initial phase, the reticle project has concentrated on working with the mask and blank suppliers to assure timely
availability of reticles for the ADT. An overview is given of the other reticle related activities, as well as first results of
a defect printability assessment by simulation and a study of blank reflectivity control. Guidance is given to the EUV
mask infrastructure to assure timely availability of reticles, first for the alpha demo tool (ADT), but also in preparation
for future use of EUV lithography in production. In the ADT assessment project, simulation studies are reported aimed at
the development of optical correction for flare and reticle shadowing effects. The impact of flare and shadowing effects
are well understood Strategies for flare mitigation and shadowing effect correction are proposed.
With first full-field exposure tools for extreme ultraviolet lithography (EUVL) materializing, the present paper intends to
review the status of the EUV mask infrastructure to assure timely availability of reticles, first for the alpha demo tool
(ADT), but also in preparation for future use of EUV lithography in production. First, the major requirements such as
low thermal expansion substrates, multilayer reflectivity control, flatness requirements and absorber related requirements
are reviewed and motivated. In a second part the status of the infrastructure is reviewed, and it is shown that both for
mask blank suppliers and mask shops full-field EUV reticles bring new challenges. Because the mask blank
infrastructure is critical to the success of EUV lithography, IMEC has addressed blanks vendors (together with ASML)
and mask shops, to get first feedback on the challenges recognized for production tool masks, exploring key parameters
that impact overlay and imaging. IMEC has prepared to obtain reticles with an identical layout from multiple mask
shops. The present paper gives a snapshot of the available EUV mask infrastructure, with a focus on blank related
aspects, in an anonymous way. It is a report of work in progress.
IMEC has started an EUV lithography research program based on ASMLs EUV full field scanner, the Alpha Demo Tool
(ADT). Currently, the ADT is in the final phase of installation. The program focuses on three main projects: EUV
resists, EUV reticles and assessment of the ADT performance. The intent of this program is to help improve and
establish the necessary mask and resist infrastructure. In this paper, the status and the progress of the program is
reviewed. In preparation for a resist process for the ADT, interference lithography has been used to track the progress of
resist performance. Steady progress in resist development is seen, especially in terms of resolution, as some materials
are now able to resolve 25nm HP. In its initial phase, the reticle project has concentrated on working with the mask and
blank suppliers to assure timely availability of reticles for the ADT. An overview is given of the other reticle related
activities, as well as first results of a defect printability study by simulation. In the ADT assessment project, simulation
studies are reported aimed at the development of optical correction for flare and reticle shadowing effects. The impact of
flare and shadowing effects are well understood and strategies for flare mitigation and shadowing effect correction are
The 38nm and 32nm lithography nodes are the next major targets for optical lithography on the Semiconductor Industry Roadmap. The recently developed water-based immersion lithography using ArF illumination will be able to provide an optical solution for lithography at the 45nm node, but it will not be able to achieve the 38nm or the 32nm nodes as currently defined. To achieve these next lithographic nodes will require new, very high refractive index fluids to replace the water used in current immersion systems. This paper describes tests and experiments using an interference immersion lithography test jig to develop key technology for the 32nm node. Interference imaging printers have been available for years, and with the advent of Immersion Lithography, they have a new use. Interference immersion image printing offers users a rapid, cost-effective way to develop immersion lithography, particularly at extremely high resolutions. Although it can never replace classical lens-based lithography systems for semiconductor device production, it does offer a way to develop resist and fluid technology at a relatively low cost. Its simple image-forming format offers easy access to the basic physics of advanced imaging. Issues such as: Polarization of the image forming light rays; Fluid/resist interaction during exposure; Topcoat film performance; and the Line Edge Roughness (LER) of resists at extremely high resolutions can all be readily studied. Experiments are described and results are provided for work on: 32nm imaging tests; high refractive index fluid testing using 193nm wavelength at resolutions well beyond current lens-based system capabilities; and polarization configuration testing on 45nm, 38nm, and 32nm L/S features. Results on the performance of resists and topcoats are reported for 32nm L/S features.
Designing and operating exposure tools with a stable imaging performance becomes increasingly challenging as the exposure wavelength is decreased to improve resolution capabilities. At a wavelength of 157 nm, light is highly absorbed by most materials. In addition, the high photon energies readily induce photochemical degradation of the majority of organic materials. As a result many of the materials in the optical path of 157 nm exposure tools have been replaced and more stringent controls on the purge gas quality have been introduced. As the recipient of the first full field 157 nm scanners to be installed in the field, IMEC has implemented a tool-monitoring program to assess the performance of the exposure tool. The assessment includes characterization of the baseline operating conditions of the scanner and the evaluation of any potential trends in performance related to environmental interactions. This paper describes the techniques used to monitor the tool and reports on the results obtained during the initial months of tool operation.
This paper presents results of monitoring and control of contaminants in an ASML MS-VII 157nm full-field exposure tool at IMEC, as verified lithographically in terms of field uniformity, lens transmission, CD uniformity, and scattered light. The daily contamination monitoring system utilizes in-line photo-ionization detector, oxygen and moisture analyzers, as well as chemiluminescent detector, and gas chromatograph that is coupled to a mass spectrometer. On a monthly basis, contamination monitoring was performed with thermal desorption-gas chromatographi/mass spectrometric techniques. The following four locations within the optical path of the MS-VII are monitored: source optic assembly, condenser lens optic, 1X relay station, and projection optics box. Contamination control is realized in the system with an on-board purge control unit, which is equipped with gas purifiers that remove contaminants such as H2O, O2, CO, CO2, hydrocarbons, H2, and sulfur compounds. All the observed contaminants have been trending within expected values and no contamination-related tool performance degradation has been observed. The excursions observed in the contaminant concentrations are coincident with tool downtime/maintenance events. Siloxane levels appear to be consistently below 50 ppt in all the monitored locations within the optical path of the tool, except on one occasion when it reached 90 ppt in the projection optics. Volatile organic compounds (VOCs) concentration within the MS-VII enclosure show a stable background level of around 10-25 ppb during weekends and levels of 45-60 ppb (during working days). VOCs concentration variations inside the MS-VII enclosure during the working days correlate well with activities inside the clean room. Air recirculation and low intake of fresh air inside the MS-VII tend to slow down the speed with which the VOCs levels decreases to stable background level, whenever there was a major upward excursion in their concentration. Average light intensity through the projection optics correlates well with oxygen concentration. The average light intensity transmission through the PO lens has shown a steady increase over time due to in-situ laser cleaning with oxygen.
157nm lithography is currently considered as the main technology for the manufacturing of critical 65nm node layers and beyond. After a number of potential show stoppers of 157nm have been removed in the last three years, the final phase of development will now start based on the first full-field step and scan exposure systems, that will be inserted in the next 6 months. This paper describes the status and progress of the IMEC 157nm program, that is aiming to remove the remaining 157nm engineering challenges. Despite the fact that the first full field scanner (ASML Micrascan VII) will ship next month to IMEC, the investigation on a number of full-field issues already started. Results on reticle handling including vacuum ultra violet cleaning, on hard pellicle printing and on 157nm resist full field patterning are discussed in this paper.