Device fabrication based on top-down approach will reach its limit due to difficulties in patterning and processes below 10 nm node. The bottom-up approach using self-assembled materials and processes can be a viable candidate for further device scaling, but the fabrication processes are mostly not compatible with current device fabrication. In this presentation, device fabrication strategy for next-generation data-storage devices will be discussed in detail based on self-assembled materials and processes. The emphasis is placed on compatibility with current device fabrication strategies. Ordered array of various materials and systems based on bottom-up nanotechnology can be utilized as the charge storage layer for memory devices and the templates for nanoscale device fabrication. Novel device applications, for example, printed/flexible/transparent electronic devices, will be explored based on the self-assembly processes.
Conference Committee Involvement (1)
Hybrid Memory Devices and Printed Circuits 2017
10 August 2017 | San Diego, California, United States