Jangho (Jerry) Shin is presently a senior field apps engineer at ASML Korea. He was a researcher/manager at Samsung semiconductor R&D and is a Senior member of SPIE. Dr. Shin received his PhD in electrical and computer engineering from the University of Wisconsin at Madison in 2003.
The use of computational inspection to identify process window limiting hotspots and predict sub-15nm defects with high capture rate
Application results of lot-to-lot high-order and per-shot overlay correction for sub-60-nm memory device fabrication
Application results of lot-to-lot high-order overlay correction for sub-60-nm memory device fabrication
Measurement technique of nontelecentricity of pupil-fill and its application to 60 nm NAND flash memory patterns