Dr. Janko Versluijs Profile

Dr. Janko Versluijs

at IMEC

SPIE Involvement:

Author

Publications (17)

PROCEEDINGS ARTICLE | March 23, 2018

Electrical comparison of iN7 EUV hybrid and EUV single patterning BEOL metal layers

Proc. SPIE. 10583, Extreme Ultraviolet (EUV) Lithography IX

KEYWORDS: Optical lithography, Etching, Metals, Copper, Resistance, Photomasks, Extreme ultraviolet, Critical dimension metrology, Semiconducting wafers, Tin

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PROCEEDINGS ARTICLE | March 20, 2018

Exploration of BEOL line-space patterning options at 12 nm half-pitch and below

Proc. SPIE. 10589, Advanced Etch Technology for Nanopatterning VII

KEYWORDS: Oxides, Etching, Metals, Dielectrics, Scanning electron microscopy, Photoresist materials, Line edge roughness

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PROCEEDINGS ARTICLE | March 21, 2016

Analyzing block placement errors in SADP patterning

Proc. SPIE. 9779, Advances in Patterning Materials and Processes XXXIII

KEYWORDS: Semiconductors, Optical lithography, Etching, Error analysis, Manufacturing, Inspection, Scanning electron microscopy, Process control, Wafer inspection, Plasma etching, Error control coding, Semiconducting wafers, System on a chip, Overlay metrology, Device simulation, Tin

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PROCEEDINGS ARTICLE | March 17, 2015

A way to integrate multiple block layers for middle of line contact patterning

Proc. SPIE. 9428, Advanced Etch Technology for Nanopatterning IV

KEYWORDS: Oxides, Carbon, Lithography, Optical lithography, Etching, Photomasks, Double patterning technology, Semiconducting wafers, System on a chip, Tin

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SPIE Journal Paper | September 4, 2013

Key contributors for improvement of line width roughness, line edge roughness, and critical dimension uniformity: 15 nm half-pitch patterning with extreme ultraviolet and self-aligned double patterning

Xu, Kaidong , Souriau, Laurent , Hellin, David , Versluijs, Janko , Wong, Patrick , Vangoidsenhoven, Diziana , Vandenbroeck, Nadia , Dekkers, Harold , Shi, Xiaoping , Albert, Johan , Tan, Chi Lim , Vertommen, Johan , Coenegrachts, Bart , Orain, Isabelle , Kimura, Yoshie , Wiaux, Vincent , Boullart, Werner

JM3 Vol. 12 Issue 04

KEYWORDS: Line width roughness, Optical lithography, Etching, Line edge roughness, Photomasks, Silicon, Extreme ultraviolet lithography, Plasma, Plasma enhanced chemical vapor deposition, Lithography

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PROCEEDINGS ARTICLE | April 12, 2013

Simulation of spacer-based SADP (Self-Aligned Double-Patterning) for 15nm half pitch

Proc. SPIE. 8683, Optical Microlithography XXVI

KEYWORDS: Lithography, Optical lithography, Etching, Ions, Manufacturing, Extreme ultraviolet, Extreme ultraviolet lithography, Double patterning technology, Semiconducting wafers, Design for manufacturability

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PROCEEDINGS ARTICLE | March 29, 2013

15nm HP patterning with EUV and SADP: key contributors for improvement of LWR, LER, and CDU

Proc. SPIE. 8685, Advanced Etch Technology for Nanopatterning II

KEYWORDS: Lithography, Optical lithography, Etching, Silicon, Photoresist materials, Photomasks, Line width roughness, Extreme ultraviolet lithography, Line edge roughness, Plasma

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PROCEEDINGS ARTICLE | March 13, 2012

Process development using negative tone development for the dark field critical layers in a 28nm node process

Proc. SPIE. 8326, Optical Microlithography XXV

KEYWORDS: Lithography, Optical lithography, Lithographic illumination, Etching, Metals, Image processing, Photomasks, Immersion lithography, Source mask optimization, Semiconducting wafers

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The demand for ever shrinking semiconductor devices is driving efforts to reduce pattern dimensions in semiconductor lithography. In this work, the aim is to find a single patterning litho solution for a 28nm technology node using 193nm immersion lithography. Target poly pitch is 110nm and metal1 pitch is 90nm. For this, we have introduced a range of different techniques to reach this goal. At this node, it becomes essential to include the layout itself into the optimization process. This leads to the introduction of restricted design rules, together with the co-optimization of source and mask (SMO) and the use of customized illumination modes (freeform illumination sources; Flexray^TM). Also, negative tone development (NTD) is employed to further extend the applicability of 193nm immersion lithography. Traditionally, the printing of contacts and trenches is done by using a dark field mask in combination with a positive tone resist and positive tone development. The use of negative tone development enables images reversal. This allows benefiting from the improved imaging performance when exposing with bright field masks. The same features can be printed in positive tone resists and with improved process latitudes. At the same time intermediate metal (IM) layers are used to connect the front-end and back-end-of-line, resulting in huge area benefits compared to layouts without these IM layers. The use of these IM layers will not happen for the 28nm node, but is intended to be introduced towards the 20nm node, and beyond. Nevertheless, the choice was made to use this architecture to obtain a first learning cycle on this approach. In this study, the use of negative tone development is explored, and its use for the various dark field critical layers in a 28nm node process is successfully demonstrated. In order to obtain sufficiently large process windows, structures are printed larger than the designed target CD. As a consequence, a shrink of the structures needs to be applied to obtain the target CD after etch. Different shrink approaches are compared. Final results on wafer are discussed, focusing on critical layers as IM1, IM2, Via0 and Metal1.

PROCEEDINGS ARTICLE | April 8, 2011

Patterning challenges in setting up a 16nm node 6T-SRAM device using EUV lithography

Proc. SPIE. 7969, Extreme Ultraviolet (EUV) Lithography II

KEYWORDS: Lithography, Optical lithography, Etching, Photomasks, Extreme ultraviolet, Extreme ultraviolet lithography, Optical proximity correction, Critical dimension metrology, Semiconducting wafers, Fin field effect transitor

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PROCEEDINGS ARTICLE | March 23, 2011

Spacer defined double patterning for (sub-)20nm half pitch single damascene structures

Proc. SPIE. 7973, Optical Microlithography XXIV

KEYWORDS: Oxides, Carbon, Optical lithography, Etching, Scanning electron microscopy, Line width roughness, Double patterning technology, Optical alignment, Line edge roughness, Semiconducting wafers

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SPIE Journal Paper | January 1, 2009

30-nm half-pitch metal patterning using Motif^TM critical dimension shrink technique and double patterning

Versluijs, Janko , de Marneffe, Jean-Francois , Goossens, Danny , Vandeweyer, Tom , Wiaux, Vincent , Struyf, Herbert , Maenhoudt, Mireille , Brouri, Mohand , Vertommen, Johan , Kim, Jisoo , Zhu, Helen

JM3 Vol. 8 Issue 01

KEYWORDS: Etching, Critical dimension metrology, Optical lithography, Optical proximity correction, Metals, Scanning electron microscopy, Semiconducting wafers, Photomasks, Double patterning technology, Tin

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PROCEEDINGS ARTICLE | April 1, 2008

30nm half-pitch metal patterning using Moti CD shrink technique and double patterning

Proc. SPIE. 6924, Optical Microlithography XXI

KEYWORDS: Optical lithography, Etching, Metals, Dielectrics, Scanning electron microscopy, Photomasks, Double patterning technology, Optical proximity correction, Semiconducting wafers, Tin

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PROCEEDINGS ARTICLE | March 26, 2007

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Optical lithography, Atrial fibrillation, Etching, Dielectrics, Scanning electron microscopy, Photomasks, Double patterning technology, Optical proximity correction, Photoresist processing, Semiconducting wafers

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PROCEEDINGS ARTICLE | March 21, 2007

A novel plasma-assisted shrink process to enlarge process windows of narrow trenches and contacts for 45-nm node applications and beyond

Proc. SPIE. 6519, Advances in Resist Materials and Processing Technology XXIV

KEYWORDS: Lithography, Optical lithography, Etching, Polymers, Scanners, Scanning electron microscopy, Photoresist materials, Critical dimension metrology, Semiconducting wafers, 193nm lithography

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PROCEEDINGS ARTICLE | March 21, 2007

Double pattern EDA solutions for 32nm HP and beyond

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Logic, Optical lithography, Etching, Metals, Image processing, Manufacturing, Photomasks, Double patterning technology, Optical proximity correction, Electronic design automation

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The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k₁ for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k₁ for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

PROCEEDINGS ARTICLE | March 15, 2006

Early learning on hyper-NA lithography using two-beam immersion interference

Proc. SPIE. 6154, Optical Microlithography XIX

KEYWORDS: Refractive index, Prisms, Polarization, Water, Scanners, Electroluminescence, Printing, Nanoimprint lithography, Semiconducting wafers, Liquids

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PROCEEDINGS ARTICLE | May 12, 2004

Double patterning scheme for sub-0.25 k1 single damascene structures at NA=0.75, λ=193nm

Proc. SPIE. 5754, Optical Microlithography XVIII

KEYWORDS: Oxides, Etching, Copper, Resistance, Double patterning technology, Nanoimprint lithography, Critical dimension metrology, Semiconducting wafers, Overlay metrology, 193nm lithography

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Showing 5 of 17 publications

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