Dr. Jason P. Cain
Principal Member of the Technical Staff
SPIE Involvement:
Fellow status | Senior status | Conference Program Committee | Conference Chair | Conference Co-Chair | Editor | Author | Instructor
Websites:
Profile Summary

Jason Cain works in the field of Design for Manufacturability (DFM) at Advanced Micro Devices (AMD) in Austin, Texas, where he is currently Principal Member of the Technical Staff. Since joining AMD in 2004, his career has spanned several fields including lithography, semiconductor metrology, advanced process control, factory automation, optical proximity correction and resolution enhancement techniques.

In his current role, Dr. Cain is responsible for leading the DFM team to enable manufacturable test chip and product designs at leading edge technology nodes down to 5nm and beyond. Dr. Cain has published more than 40 technical papers and holds five United States patents. He received the B.S. degree in electrical engineering from Texas A&M University in 1999 and the M.S. and Ph.D. degrees in electrical engineering and computer sciences from the University of California, Berkeley in 2002 and 2004, respectively.
Publications (37)

Proceedings Article | 18 March 2019
Proc. SPIE. 10962, Design-Process-Technology Co-optimization for Manufacturability XIII
KEYWORDS: Silicon, Inspection, Diagnostics, Feature extraction, Machine learning, High volume manufacturing, Failure analysis

Proceedings Article | 10 April 2018
Proc. SPIE. 10588, Design-Process-Technology Co-optimization for Manufacturability XII
KEYWORDS: Lithography, Data modeling, Manufacturing, Feature extraction, Design for manufacturing, Machine learning, Testing and analysis, Model-based design

Proceedings Article | 4 April 2018
Proc. SPIE. 10588, Design-Process-Technology Co-optimization for Manufacturability XII
KEYWORDS: Lithography, Optical lithography, Metals, Pattern recognition, Manufacturing, Design for manufacturing, Machine learning, Image classification, Library classification systems

Showing 5 of 37 publications
Conference Committee Involvement (23)
Design-Process-Technology Co-optimization for Manufacturability XIV
23 February 2020 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXIV
23 February 2020 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XIII
27 February 2019 | San Jose, California, United States
Metrology, Inspection, and Process Control for Microlithography XXXIII
25 February 2019 | San Jose, California, United States
Design-Process-Technology Co-optimization for Manufacturability XII
28 February 2018 | San Jose, California, United States
Showing 5 of 23 published special sections
Course Instructor
SC1209: Data Analytics and Machine Learning in Semiconductor Manufacturing: Applications for Physical Design, Process and Yield Optimization
This course provides an introduction to methodologies and techniques in Data Analytics and Machine Learning, with specific applications to semiconductor manufacturing, from physical design characterization to process and yield optimization. While the growth of (Big) Data Analytics and Machine Learning continues to increase across virtually every industrial sector, the semiconductor space has seen only a modest adoption. This course aims at lowering the entry barrier, by providing both foundational and practical skills for semiconductor engineers and practitioners. Following a comprehensive survey of the state-of-the-art and current developments in Data Analytics and Machine Learning, the course describes how functional interactions and data information flows in the Design-to-Manufacturing chain can be enhanced by analytics algorithmic methodologies. Quantitative definitions of physical design space coverage and process space learning are introduced as the unifying abstraction, allowing for the construction of a computational application framework. Design-Technology-Co-Optimization (DTCO) is then extended with the novel paradigm of DFM-as-Search. Examples from this new DFM computational toolkit, are used to demonstrate how the advanced IC technology nodes (14, 10, 7 and 5nm) not only benefit from, but actually require the use of a new class of correlation extraction algorithms for heterogeneous data sets.
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