In this paper we discuss a laser focus drilling technique which has recently been developed for advanced
immersion lithography scanners to increase the depth of focus and therefore reduce process variability of contact-hole
patterns. Focus drilling is enabled by operating the lithography light-source at an increased spectral bandwidth, and has
been made possible by new actuators, metrology and control in advanced dual-chamber light-sources. We report wafer
experimental and simulation results, which demonstrate a process window enhancement for targeted device patterns.
The depth of focus can be increased by 50% or more in certain cases with only a modest reduction in exposure latitude,
or contrast, at best focus. Given this tradeoff, the optimum laser focus drilling setting needs to be carefully selected to
achieve the target depth of focus gain at an acceptable contrast, mask error factor and optical proximity behavior over
the range of critical patterning geometries. In this paper, we also discuss metrology and control requirements for the
light-source spectrum in focus drilling mode required for stable imaging and report initial trend monitoring results over
several weeks on a production exposure tool. We additionally simulate the effects of higher-order chromatic aberration
and show that cross-field and pattern-dependent image placement and critical dimension variation are minimally
impacted for a range of focus drilling laser spectra. Finally, we demonstrate the practical process window benefits and
tradeoffs required to select the target focus drilling laser bandwidth set-point and increase effectiveness of the sourcemask
solution for contact patterning.
Among the valid gate pattern strategies for the 65nm technology node, att-PSM offers the advantage in cost and mask complexity over other contenders such as complimentary alt-PSM and chromeless phase lithography (CPL). A combination of Quasar illumination and sub-resolution assist features (SRAFs) provides a through pitch solution with a common depth of focus (DOF) better than 0.25um to support the aggressive scaling in both logic and high density SRAM. A global mask-source optimization scheme is adopted to explore the multi-dimensional space of process parameters and define the best overall solution that includes scanner optics such as NA and illumination, and SRAF placement rules for 1-dimensional line and space patterns through the full pitch range. Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper. Conflict resolution and placement optimization are key to the success of implementation of SRAF to the complex 2-dimensional layouts of random logic. Reasonable CD control can be achieved based on the characterization and simulation of CD variations at different spatial and processing domains from local to across chip, across wafer, wafer-to-wafer, and lot-to-lot. Certain layout restrictions are needed for high performance devices which require a much tighter gate CD distribution. Scanner optimization and enhancement such as DoseMapper are key enablers for such aggressive CD control. The benefits, challenges, and possible extensions of this particular approach are discussed in comparison with other techniques.