Currently, CD-SEMs are the tool of choice for in-line gate length measurements for most semiconductor manufacturers. This is in large part due to their flexibility, throughput, and ability to correlate well to physical measurements (e.g., XSEM). However, scatterometry is being used by an increasing number of manufacturers to monitor and control gate lengths. But can a scatterometer measure such small critical dimensions well enough? This paper explores this question by analyzing data taken from wafers processed using 90 nm node technology. These wafers were measured after gate formation (gate final CD) using a CD-SEM as well as a scatterometer. They were then processed into the back-end-of-line and measured electrically. This electrical measurement, called L<sub>poly</sub>, is an important parametric device measurement and is used to screen product before it reaches final electrical test. It is therefore critical for the in-line metrology immediately after gate formation to have excellent correlation to L<sub>poly</sub>. Analysis shows that the scatterometer correlates well to both in-line CD-SEM measurements across multiple structures as well as electrical L<sub>poly</sub> measurements. More importantly, the scatterometer is shown to be approximately equivalent to the CD-SEM when both are correlated to L<sub>poly</sub>. Since several scatterometry targets with different pitches were measured, the amount of correlation as a function of pitch is also investigated. Because traditional methods of correlation, such as Ordinary Least Squares (OLS), have severe limitations, Total Measurement Uncertainty (TMU) analysis is used as a highly effective assessment methodology. This paper also shows how TMU analysis is used to improve the scatterometry model and understand the relative contributions from obstacles that hinder the achievement of even better correlations.
Proc. SPIE. 5038, Metrology, Inspection, and Process Control for Microlithography XVII
KEYWORDS: Semiconducting wafers, Line edge roughness, Atomic force microscopy, Scanning electron microscopy, Voltage controlled current source, Optical resolution, Manufacturing, Reticles, Edge roughness, Microelectronics
The Apparent Beam Width (ABW) total system resolution metric is part of the International SEMATECH CDSEM specification and bench marking activities. It is also used in our own CDSEM specification, evaluations, and tool maintenance activities. Our first set of ABW artifacts, constructed a few years ago, need retirement for several reasons, including: (1) their materials and dimensions no longer represent current manufacturing line samples and (2) their line edge variation is too large for current and future ABW applications. The construction and testing of a new ABW artifact will be discussed in this paper. The use of ABW as a monitor for total system resolution requires a unique set of sample characteristics, which include near vertical sidewalls, minimal top corner rounding, minimal line edge roughness (LER), and good line edge uniformity across the artifact set. Several process iterations were performed using the latest photolithographic processes whilst including numerous measurement evaluations in order to achieve these characteristics. A sampling methodology has been formulated to take advantage of the good within-field, field-to-field, and wafer-to-wafer uniformities of the artifacts. In addition to driving resolution improvements ABW also serves as a metric for tool-to-tool matching in a manufacturing environment.
Measurement using electron beam tilt has recently been highlighted as holding the promise of future sidewall angle and thickness determinations in the CD SEM in a manufacturing environment. But even before robust tilted beam measurements can be made, a thorough understanding of stray tilt, its characterization and control, is needed to provide the foundation for tilt calibrations and measurements. Stray tilt is the amount of unintended angular deviation of the electron beam from the normal to the specimen's (wafer) surface. Stray tilt is common to all SEMs used in manufacturing due to the following contributors: mechanical tolerances, acting both within the SEM column and between the SEM column and the chamber and the sample holder; and also residual and parasitic magnetic and electrostatic fields - these fields are generated both within and outside of the SEM integrated stand-alone unit. Past characterization attempts addressed this issue through an asymmetry specification. Recent data has suggested that stray tilt errors can have significant negative effects on today's critical dimension measurements, especially on a fleet of CD SEM tools with different amounts of stray tilt. This paper explores the measurement, monitoring and minimizing of stray tilt and the consequences on tool matching.
Proc. SPIE. 4689, Metrology, Inspection, and Process Control for Microlithography XVI
KEYWORDS: Critical dimension metrology, Smoothing, Scanning electron microscopy, Etching, Signal to noise ratio, Semiconducting wafers, Standards development, Transistors, Finite element methods, Process control
Automated top down critical dimension scanning electron microscopy (CD SEM) remains the tool of choice for critical dimension process control and dispositioning. Although CD SEMs have limitations, their combination of throughput, resolution, precision, ability to measure any feature of interest and automation has been unmatched in recent years. As geometries shrink in non-uniform ways and manufacturing processes become more complicated, questions continue to recur concerning the degree of correlation between post- develop and post-etch CD measurements. For the particularly critical processing steps of forming the transistor gate, the correlation of these measurements to subsequent electrical measurements is also of major concern. Can CD SEM measurement parameters be better optimized to improve these correlations. This study attempts to answer this question by gathering CD SEM raw waveforms and AFM linescans at gate develop and etch and comparing to electrical test measurements for an advanced device fabrication process. Optimal settings of the CD algorithms working on the waveforms are then sought to improve these correlations. The tradeoff with measurement precision will also be discussed.