Over the years, lithography engineers continue to focus on CD control, overlay and process capability to
meet current node requirements for yield and device performance. Use of ArFi lithography for advanced
process nodes demands challenging patterning budget improvements in the range of 1/10 nm especially
for interconnect layers.(1) Previous experimental and simulation based investigations into the effects of
light source bandwidth on imaging performance have provided the foundation for this work.(2-6) The
goal from the light source manufacturer is to further enable capability and reduce variation through a
number of parameters.(7-10)
In this study, the authors focus on the increase in image contrast that Source Mask Optimization (SMO)
and Optical Proximity Correction (OPC) models deliver when comparing 300 fm and 200 fm light source
E95% bandwidth. Using test constructs that follow current N7 / N5 ground rules and multiple pattern
deconstruction rules, improvements in exposure latitude (EL), critical dimension (CD) and mask error
enhancement factor (MEEF) performance are observed when SMO and OPC are optimized for 200 fm
light source bandwidth when compared with the standard 300 fm bandwidth. New SMO-OPC flows will
be proposed that users can follow to maximize process benefit. The predicted responses will be
compared with the experimental on wafer responses of 7 nm features to lower light source bandwidth.
Fast and robust metrologies for retrieving large amount of accurate wafer data is the key to meet the ever stricter semiconductor manufacturing process control such as critical dimension (CD) and overlay as the industry moving towards 22 nm or smaller designs. Scatterometry emerges due to its non-destructivity and rapid availability for accurate wafer data. In this paper we simulate the ability of a new scatterometry method to show its accurate control over lithography model and OPC model calibrations. The new method directly utilizes scattering signals of scatterometry to control the process instead of using numerically analyzed dimensional parameters such as CD and side wall angle (SWA). The control can be achieved by optimizing the scattering signal of one process by tuning numerical aperture (NA), sigma, or lens aberration to match the signal of the target process. In this work only sigma is used for optimization. We found that when the signals of both processes are matched with minimized optimization error, CD of the grating profiles on the wafers are also minimized. This result enables valid lithography process control and model calibration with the new method.
As the feature sizes continue to shrink, more overlay metrology data are needed to meet
tighter overlay specifications which ensure high device yield. This study investigates the
advantages of process corrections to overlay errors using various reduced measurement
wafer schemes, and the improvement in yield that is realized using optimized overlay
correction models. The capacitor layer of a 4x node DRAM product is chosen for
verifying the sampling schemes in the experiment, because overlay errors of this layer are
sensitive to device yield. The test wafers are split into five groups; four groups are
sampled using various schemes and overlay correction models, and one group has a
programmed overlay error. The post-correction overlay residuals in full wafer, baseline
sampling and optimized sampling agree closely with predictions that are based on raw
measurements. A scheme with iHOPC (intrafield high order process correction) partial
third-order terms with a CPE (correction per exposure) function provides the best overlay
performance. The averaged device yields of reduced sampling schemes are comparable
with those of the full wafer scheme, however the reduction of the number of
measurements that is made in optimized sampling reduce the metrology tool time by 26%
from that required using the current scheme of factory. Therefore, the cost of metrology
can be further reduced by applying the proposed optimized sampling map in the routine
operations of fab.
Optical scatterometry is crucial to advanced nodes due to its ability of non-destructively and rapidly retrieving accurate
3D profile information.1, 2, 3 In recent years, an angle-resolved polarized reflectometry-based scatterometry which can
measure critical dimensions, overlay, and focus in single shot has been developed.4, 6, 20 In principle, a microscope
objective collects diffracted light, and pupil images are collected by a detector. For its application of calibrating
lithography models, the pupil images are fit to a database pre-characterized usually by rigorous electromagnetic
simulation to estimate dimensional parameters of developed resist profiles.5 The estimated dimensional parameters can
then be used for lithography model calibration. In this work, we propose a new method which directly utilizes the pupil
images to calibrate lithography models without needing dimensional parameter estimation. To test its feasibility and
effectiveness by numerical simulation, a reference lithography process model is first constructed with a set of parameter
values complying with ITRS. A to-be-calibrated process model is initialized with a different set of parameter values from
those of the reference model. Rigorous electromagnetic simulation is used to obtain the pupil images of the developed
resist profiles predicted by both process models. An optimization algorithm iteratively reduces the difference between
the pupil images by adjusting the set of parameter values of the to-be-calibrated process model until the pupil image
difference satisfies a predefined converging criterion. This method can be used to calibrate both rigorous first-principle
models for process and equipment development and monitoring, and fast kernel-based models for full-chip proximity
effect simulation and correction. Preliminary studies with both 1D and 2D aperiodic and periodic layouts indicate that
when the pupil image difference is minimized, the lithography model can be accurately calibrated.
The fingerprint of the optical proximity effect, OPE, is required to develop each process node's optical proximity
correction (OPC) model. This model should work equally well on different exposure systems. However, small
differences in optical and mechanical properties in the lithographic system can lead to a different CD characteristic for a
given OPC. It becomes beneficial to match the OPE of one scanner to the scanner population in a fab. Here, we focus on
aspects of angle resolving scatterometry metrology used for OPE matching of two XT:1700i scanners and compare those
to SEM metrology. The capability of the scatterometry tool for monitoring the stability of OPE is evaluated.
Scatterometry allows measuring the side wall angle, SWA, of a resist profile and this can be used as a measure for focus.
Here, focus comparison by SWA is included into the matching process. For the application used here, the residual RMS
mismatch through pitch for scatterometry could be reduced to 0.2nm compared to 0.5nm for CD-SEM.
Processes of 65nm node are applied on a scanner (TWINSCAN XT1700i) for this experiment. The five adjustable scanner parameters investigated are dose, focus scan range, NA, σ_width, and
σ_center of the illumination pupil. The test reticle contains a range of pitches, each with a variety of
biases sufficient for selecting the target CD at each pitch. It can be used for exposing patterns for
both CD SEM and scatterometry. The minimum and maximum pitches of the 1D line/space pattern
are 135 and 500nm, respectively, and no assist feature is added for the isolated pitches. Seventeen
pitches are selected for generating the through-pitch curve, and they are the most sensitive ones to
this illumination setting.
Two metrology tools are used to measure the printed features, i.e. CD SEM and scatterometry.
MCD (Middle CD) measured by scatterometry is compared with CD SEM data for the OPE curve.
A very consistent offset between two metrologies is presented through the pitches; the R2 value is
greater than 0.98 for point to point of CD SEM versus MCD correlation. In addition to the CD
measurements, scatterometry provides SWA information, which is verified to correlate linearly with
focus variations. Based on the metrology data, results of this study demonstrate that the OCD data
are as reliable as the CD SEM measurements.
The fingerprint of optical proximity effect, OPE, is required to develop each process node's optical proximity correction
(OPC) model. The OPC model should work equally well on exposure systems of the type on which the model was
developed and of different type. Small differences in optical and mechanical scanner properties can lead to a different
CD characteristic for a given OPC model. It becomes beneficial to match the OPE of one scanner to the scanner
population in a fab. Here, we report on a matching technique based on measured features in resist employing either CDSEM
or scatterometry. We show that angle resolving scatterometry allows improving the metrology throughput and
repeatability. The sensitivity of the CD as a function of the scanner adjustments and the effect of scanner tuning can be
described more precisely by scatterometry using an identical number of printed features for measurement. In our
example the RMS deviation between the measured and the predicted tuning effect of scatterometry is 0.2 nm compared
to 0.8 nm of CD-SEM allowing to set tighter matching targets.
The authors will explore the possible contact hole lithography solutions for the future technology nodes, from 90 nm
down to 32 nm half-pitch (HP) in this paper. The special emphasis will be on the logic application because of the lack of
a strong resolution enhancement technique (RET) for the random hole layouts. The use of illumination optimization,
focus drilling can extend the projection optical lithography down to near 60 nm HP. The adoption of pitch split double
exposure technique is needed to provide a robust manufacturing process window to further extend to around 50 nm HP.
To further shrinking the design rule, a double patterning is need after the pitch split. The pitch split double patterning
technique reaches its limit around 40 - 45 nm HP. The desire to not limit the integrated circuit (IC) design requires the
lithography process k1 to be as high as possible. The random logic contact hole application is well suited for EUV
lithography for 35 nm HP and below because of the high k1 process and a potential for high productivity of a mask based
lithography. The pattern density of contact hole masks would not require a stringent mask defect requirement, and
moreover, the EUV's relatively higher system flare does not have a significant impact on imaging. Actual EUV data and
calibrated simulations will be used to demonstrate that EUV can provide a robust process window.
Immersion exposure system with the numerical aperture (NA) greater than unity effectively extends the printing resolution limit without the need of shrinking the exposure wavelength. From the perspective of imaging contact hole mask, we are convinced that a mature ArF immersion exposure system will be able to meet 45nm node manufacturing requirement. However, from a full-chip mask data processing point of view, a more challenging question could be: how to ensure the intended RET mask to best achieve a production worthy solution? At 45nm, we are using one-fourth of the exposure wavelength for the patterning; there is very little room for error. For full-chip, especially for contact hole mask, we need a robust RET mask strategy to ensure sufficient CD control. A production-worthy RET mask technology should have good imaging performance with advanced exposure system; and, it should base on currently available mask blank material and be compatible with the existing mask making process.
In this work, we propose a new type of contact hole RET masks that is capable of 45nm node full-chip manufacturing. Three types of potential RET masks are studied. The 1st type is the conventional 6% attenuated PSM (attPSM) with 0-phase Scattering Bars (SB). The 2nd type is to use CPL mask with both 0- and π-phase SB, and their relative placements are based on interference mapping lithography (IML) under optimized illumination. The 3rd type, here named as 6% CPL, can be thought of as a CPL mask type with 6% transmission on the background but with π-phase SB only. Of those three RET masks, 6% CPL mask has the best performance for printing 45nm contact and via masks.
To implement 6% CPL for contact and via mask design, we study several critical process steps starting from the illumination optimization, model-based SB OPC, 3D mask effect, quartz etch depth optimization, side-lobe printability verification, and then to the mask making flow. Additionally, we investigate printability for through-pitch contact array, and random contact design. To characterize the printing performance, we use MEEF, and process window (PW) to analyze the simulation data. We conclude that the 45nm node contact hole imaging is well within reach using a mature ArF immersion exposure tool with a robust and well integrated RET mask scheme.
Interference Mapping Lithography (IML) is the latest innovation to extend optical imaging solutions to contact hole printing. This approach optimizes the placement of assist features to enhance the process window of the contact hole layer. However, the printing of assist features is a concern of the IML technology. This study presents a checking scheme to analyze the assist feature printing using the aerial image simulation. If the checking method confirms the assist feature printing, the adjustment algorithm optimizes the assist feature design. An example of a 5×5 array pattern is employed to demonstrate the methodologies; which avoid assist feature printing yet still improve the process window by adding the appropriate assist feature design.