This work presents a new continuous-time equalization approach to overcome the limited bandwidth of integrated CMOS photodetectors. It is based on a split-path topology that features completely decoupled controls for boosting and gain; this capability allows a better tuning of the equalizer in comparison with other architectures based on the degenerated differential pair, which is particularly helpful to achieve a proper calibration of the system. The equalizer is intended to enhance the bandwidth of CMOS standard n-well/p-bulk differential photodiodes (DPDs), which falls below 10MHz representing a bottleneck in fully integrated optoelectronic interfaces to fulfill the low-cost requirements of modern smart sensors. The proposed equalizer has been simulated in a 65nm CMOS process and biased with a single supply voltage of 1V, where the bandwidth of the DPD has been increased up to 3 GHz.
A multi-rate low-voltage continuous-time adaptive equalizer is presented in this paper. It was designed to compensate the high-frequency attenuation of a 50-m 1-mm core step-index plastic optical fiber (SI-POF) for input data ranges from 400 Mbps up to 1.25 Gbps. The equalization is based on the power-spectrum technique and the circuit operates with a single supply voltage of 1 V. The structure is formed by two loops which do not interact with each other; one loop adapts to changes in the channel length and the other in the data rates.
We present a low-voltage merged CDR and cntinuous-time adaptive equalizer capable to compensate the attenu- ation of a SI-POF channel while at the same time synchronizing and regenerating the incoming signal in a single stage. The system operates at 1.25 Gbps for NRZ modulation through a 50-m SI-POF channel and it is designed in standard 0.18-μm CMOS fed at 1 V with a power consumption of 43.4 mW.
This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.