Mr. Jean-Christophe Michel Profile

Jean-Christophe Michel

at STMicroelectronics

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Publications (6)

SPIE Journal Paper | 10 April 2015

Patterning critical dimension control for advanced logic nodes

Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud

JM3, Vol. 14, Issue 02, 021103, (April 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.2.021103

KEYWORDS: Semiconducting wafers, Optical lithography, Critical dimension metrology, Process control, Photomasks, Etching, Logic, Metrology, Lithography, Optical proximity correction

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Proceedings Article | 31 March 2014 Paper

Wafer sub-layer impact in OPC/ORC models for advanced node implant layers

Jean-Christophe Le-Denmat, Jean-Christophe Michel, Elodie Sungauer, Emek Yesilada, Frederic Robert, Song Lan, Mu Feng, Lei Wang, Laurent Depre, Sanjay Kapasi

Proceedings Volume 9052, 90520D (2014) https://doi.org/10.1117/12.2047115

KEYWORDS: Semiconducting wafers, Data modeling, Optical proximity correction, Calibration, Optical lithography, Wafer-level optics, Scanning electron microscopy, Photomasks, Modulation, Lithography

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Proceedings Article | 31 March 2014 Paper

Fast integral rigorous modeling applied to wafer topography effect prediction on 2x nm bulk technologies

J.-C. Michel, J.-C. Le Denmat, A. Tishchenko, Y. Jourlin

Proceedings Volume 9052, 905223 (2014) https://doi.org/10.1117/12.2045899

KEYWORDS: Semiconducting wafers, Global system for mobile communications, Optical lithography, Photomasks, Finite-difference time-domain method, Computer simulations, Silicon, Lithography, Wafer-level optics, Optical proximity correction

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Reflection by wafer topography and underlying layers during optical lithography can cause unwanted overexposure in the resist [1]. In most cases, the use of bottom anti reflective coating limits this effect. However, this solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under development to simulate and correct wafer topographical effects [2], [3]. For ionic implantation source drain (SD) photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer wafer topography simulation. A presentation of a fast rigorous Maxwell’s equation solving algorithm integrated into a photolithography proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally, integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.

Proceedings Article | 1 October 2013 Paper

Full chip implant correction with wafer topography OPC modeling in 2x nm bulk technologies

J-C. Michel, J-C. Le Denmat, E. Sungauer, F. Robert, E. Yesilada, A-M. Armeanu, J. Entradas, J. Sturtevant, T. Do, Y. Granik

Proceedings Volume 8880, 88801J (2013) https://doi.org/10.1117/12.2027291

KEYWORDS: Semiconducting wafers, Optical proximity correction, Data modeling, Silicon, Calibration, 3D modeling, Photomasks, Modulation, Scanning electron microscopy, Active optics

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Proceedings Article | 12 April 2013 Paper

Wafer sub-layer impact in OPC/ORC models for 2x nm node implant layers

Jean-Christophe Le-Denmat, Catherine Martinelli, Elodie Sungauer, Jean-Christophe Michel, Emek Yesilada, Frederic Robert

Proceedings Volume 8683, 868314 (2013) https://doi.org/10.1117/12.2011424

KEYWORDS: Photomasks, Semiconducting wafers, Optical proximity correction, Silicon, Optical lithography, Calibration, Lithography, Defect inspection, Inspection, Scanning electron microscopy

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Proceedings Article | 12 April 2013 Paper

Wafer topography modeling for ionic implantation mask correction dedicated to 2x nm FDSOI technologies

Jean-Christophe Michel, Jean-Christophe Le Denmat, Elodie Sungauer, Frédéric Robert, Emek Yesilada, Ana-Maria Armeanu, Jorge Entradas, John Sturtevant, Thuy Do, Yuri Granik

Proceedings Volume 8683, 86830I (2013) https://doi.org/10.1117/12.2011412

KEYWORDS: Silicon, Semiconducting wafers, Oxides, Data modeling, Calibration, 3D modeling, Scanning electron microscopy, Photomasks, Process modeling, Optical lithography

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Showing 5 of 6 publications

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