Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
From 28 nm technology node and below optical proximity correction (OPC) needs to
take into account light scattering effects from prior layers when bottom anti-reflective coating
(BARC) is not used, which is typical for ionic implantation layers. These effects are complex,
especially when multiple sub layers have to be considered: for instance active and poly structures
need to be accounted for.
A new model form has been developed to address this wafer topography during model
calibration called the wafer 3D+ or W3D+ model. This model can then be used in verification
(using Tachyon LMC) and during model based OPC to increase the accuracy of mask correction
and verification. This paper discusses an exploration of this new model results using extended
wafer measurements (including SEM). Current results show good accuracy on various
Reflection by wafer topography and underlying layers during optical lithography can cause unwanted
overexposure in the resist . In most cases, the use of bottom anti reflective coating limits this effect. However, this
solution is not always suitable because of process complexity, cost and cycle time penalty, as for ionic implantation
lithography process in 28nm bulk technology. As a consequence, computational lithography solutions are currently under
development to simulate and correct wafer topographical effects , . For ionic implantation source drain (SD)
photolithography step, wafer topography influences resulting in implant pattern variation are various: active silicon
areas, Poly patterns, Shallow Trench Isolation (STI) and topographical transitions between these areas. In 28nm bulk SD
process step, the large number of wafer stack variations involved in implant pattern modulation implies a complex
modeling of optical proximity effects. Furthermore, those topography effects are expected to increase with wafer stack
complexity through technology node downscaling evolution. In this context, rigorous simulation can bring significant
value for wafer topography modeling evolution in R and D process development environment. Unfortunately, classical
rigorous simulation engines are rapidly run time and memory limited with pattern complexity for multiple under layer
wafer topography simulation.
A presentation of a fast rigorous Maxwell’s equation solving algorithm integrated into a photolithography
proximity effects simulation flow is detailed in this paper. Accuracy, run time and memory consumption of this fast
rigorous modeling engine is presented through the simulation of wafer topography effects during ionic implantation SD
lithography step in 28nm bulk technology. Also, run time and memory consumption comparison is shown between
presented fast rigorous modeling and classical rigorous RCWA method through simulation of design of interest. Finally,
integration opportunity of such fast rigorous modeling method into OPC flow is discussed in this paper.
Ionic implantation photolithography step considered to be non critical started to be influenced by unwanted
overexposure by wafer topography with technology node downscaling evolution , . Starting from 2xnm technology
nodes, implant patterns modulated on wafer by classical implant proximity effects are also influenced by wafer
topography which can cause drastic pattern degradation , . This phenomenon is expected to be attenuated by the
use of anti-reflecting coating but it increases process complexity and involves cost and cycle time penalty. As a
consequence, computational lithography solutions are currently under development in order to correct wafer
topographical effects on mask . For ionic implantation source Drain (SD) on Silicon bulk substrate, wafer topography
effects are the consequence of active silicon substrate, poly patterns, STI stack, and transitions between patterned wafer
In this paper, wafer topography aware OPC modeling flow taking into account stack effects for bulk technology
is presented. Quality check of this full chip stack aware OPC model is shown through comparison of mask computational
verification and known systematic defectivity on wafer. Also, the integration of topographical OPC model into OPC
flow for chip scale mask correction is presented with quality and run time penalty analysis.
From 28nm technology node and below, Optical Proximity Correction (OPC) needs to take into account light scattering effects from prior layers when bottom anti-reflective coating (BARC) is not used, which is typical for implant layers. In this paper, we implement a sub-layer aware simulation method into a verification tool for Optical Rule Check (ORC) that is used on full 28nm test chip. The sub-layer aware verification can predict defects that are missed by standard ORC. SEM-CD review and defectivity analysis were used to confirm the validity of the sub-layer aware model on wafer.
Reflection by wafer topography and underlying layers during optical lithography can cause unwanted exposure in the resist . This wafer stack effect phenomenon which is neglected for larger nodes than 45nm, is becoming problematic for 32nm technology node and below at the ionic implantation process. This phenomenon is expected to be attenuated by the use of anti-reflecting coating but increases process complexity and adds cost and cycle time penalty. As a consequence, an OPC based solution is today under evaluation to cope with stack effects involved in ionic implantation patterning  . For the source drain (SD) ionic implantation process step on 28nm Fully Depleted Silicon-on-Insulator (FDSOI) technology, active silicon areas, poly silicon patterns, Shallow Trench Isolation (STI), Silicon-on-Insulator (SOI) areas and the transitions between these different regions result in significant SD implant pattern critical dimension variations. The large number of stack variations involved in these effects implies a complex modeling to simulate pattern degradations. This paper deals with the characterization of stack effects on 28nm node using SOI substrates. The large number of measurements allows to highlight all individual and combined stack effects. A new modeling flow has been developed in order to generate wafer stack aware OPC model. The accuracy and the prediction of the model is presented in this paper.