The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
Resolution Enhancement Techniques (RET) are inherently design dependent technologies. To be successful the RET strategy needs to be adapted to the type of circuit desired. For SOC (system on chip), the three main patterning constraints come from:
-Static RAM with very aggressive design rules specially at active, poly and contact
-transistor variability control at the chip level
The development of regular layouts, within the framework of DFM, enables the use of more aggressive RET, pushing the required k1 factor further than allowed with existing RET techniques and the current wavelength and NA limitations. Besides that, it is shown that the primary appeal of regular design usage comes from the significant decrease in transistor variability. In 45nm technology a more than 80% variability reduction for the width and the length of the transistor at best conditions, and more than 50% variability reduction though the process window has been demonstrated. In addition, line-end control in the SRAM bitcell becomes a key challenge for the 32nm node. Taking all these constraints into account, we present the existing best patterning strategy for active and poly level of 32nm :
-dipole with polarization and regular layout for active level
-dipole with polarization, regular layout and double patterning to cut the line-end for poly level.
These choices have been made based on the printing performances of a 0.17&mgr;m<sup>2</sup> SRAM bitcell and a 32nm flip-flop with NA 1.2 immersion scanner.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout
dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must
guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification
methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily
based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these
simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist,
they have often a large number of parameters to fit and suffer from long computing times to execute the simulations.
Simplified resist models are thus needed to enhance run-time computing during simulation.
The objective of this study is to test the predictability of such resist models across the process window. Two
different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The
second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold
to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific
simulations obtained with the two different techniques are compared against experimental results.
Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows.
For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.
The 65nm and 45nm device generations will be used to manufacture large designs using complex patterning processes in combination with exotic model-based or rule-based RETs’ scenarios. The lithography for these generations will operate in the low k1 regime value resulting in small process window and tight overlay requirements. Therefore, the potential for having yield limiting errors due to RET-process-design interactions is significantly higher than with the 130nm generation.
Additionally, the high cost of reticles and the large number of process layers make it quite important to catch these costly errors.
Optical Rule Checking (ORC) is an effective way to predict failure on wafer shapes. Used in addition to Optical Proximity Correction, it can help to reduce failures affecting yield in manufacturing. Thus, due to the inter-layer complexity of processes and RET, the necessity to check accurately particular areas which could generate costly errors is growing:
Here are some examples: 1) Low metal-contact or metal-via overlaps, 2) Small poly extension past active area, 3) Low overlap between poly and contact layers, and 4) Dual exposure techniques for single layer patterning.
The main difficulty in current implementation of multiple layer RET verification is the trade off between accuracy vs. runtime vs. fault coverage.
In this paper we will demonstrate how based on this trade off we can enhance our final printed results by accurately targeting the most likely failure mechanism on multiple layer processes check in a production environment (90nm node product layout). Finally we will show how ORC in a multiple layer check is going to help detect faults and overlay sensitive areas so as to secure process weakness areas.
We will compare several softwares where such a methodology is applied and attend to propose a post OPC verification strategy to obtain a more robust manufacturing process.
In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance:
1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects.
2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples:
-design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor.
-Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.
As lithography and other patterning processes become more complex and more non-linear with each generation, the task of physical design rules necessarily increases in complexity also. The goal of the physical design rules is to define the boundary between the physical layout structures which will yield well from those which will not. This is essentially a rule-based pre-silicon guarantee of layout correctness. However the rapid increase in design rule requirement complexity has created logistical problems for both the design and process functions. Therefore, similar to the semiconductor industry's transition from rule-based to model-based optical proximity correction (OPC) due to increased patterning complexity, opportunities for improving physical design restrictions by implementing model-based physical design methods are evident. In this paper we analyze the possible need and applications for model-based physical design restrictions (MBPDR). We first analyze the traditional design rule evolution, development and usage methodologies for semiconductor manufacturers. Next we discuss examples of specific design rule challenges requiring new solution methods in the patterning regime of low K1 lithography and highly complex RET. We then evaluate possible working strategies for MBPDR in the process development and product design flows, including examples of recent model-based pre-silicon verification techniques. Finally we summarize with a proposed flow and key considerations for MBPDR implementation.
As lithography continues to increase in difficulty with low k1 factors, and ever-tighter process margins, model-based optical proximity correction (OPC) is being used for the majority of patterning layers. As a result, the engineering effort consumed by the development and calibration of OPC models is continuing to increase at an alarming rate. One of the major focal points of this effort is the increasing emphasis on improving the accuracy of the model-based OPC corrections. One of the major contributors to final OPC accuracy is the quality of the resist model. As a result of these trends, the number of sample points used to calibrate OPC models is increasing rapidly from generation to generation. However, this increase is largely due to an antiquated approach to the construction of these calibration sets, focusing on structure variations. In this study, a new approach to the calibration of a resist model will be proposed based upon the location of calibration structures within the actual resist space over which the resist model is expected to be predictive.
It is becoming more and more difficult to ensure robust patterning after OPC due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. The techniques of Mask Rule Checking (MRC) and Optical Rule Checking (ORC) have become mandatory tools for ensuring that OPC delivers robust patterning. However the first method relies on geometrical checks and the second one is based on a model built at best process conditions. Thus those techniques do not have the ability to address all potential printing errors throughout the process window (PW). To address this issue, a technique known as Critical Failure ORC (CFORC) was introduced that uses optical parameters from aerial image simulations. In CFORC, a numerical model is used to correlate these optical parameters with experimental data taken throughout the process window to predict printing errors. This method has proven its efficiency for detecting potential printing issues through the entire process window . However this analytical method is based on optical parameters extracted via an optical model built at single process conditions. It is reasonable to expect that a verification method involving optical models built from several points throughout PW would provide more accurate predictions of printing errors for complex features. To verify this approach, compact optical models similar to those used for standard OPC were built and calibrated with experimental data measured at the PW limits. This model is then applied to various test patterns to predict potential printing errors. In this paper, a comparison between these two approaches is presented for the poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two techniques are compared with experimental results. The details of implementing these two techniques on full product layouts are also included in this study.