Mr. Jean-Damien Chapon Profile

Jean-Damien Chapon

at STMicroelectronics

SPIE Involvement:

Author

Publications (17)

Proceedings Article | 20 March 2020 Presentation + Paper

Run to run and model variability of overlay high order process corrections for mean intrafield signatures

Benjamin Duclaux, Maxime Gatefait, Olivier Mermet, Jean-Damien Chapon

Proceedings Volume 11325, 113251K (2020) https://doi.org/10.1117/12.2551062

KEYWORDS: Semiconducting wafers, Overlay metrology, Reticles, Scanners, Metrology, Data modeling, Sensors, Data corrections, Process modeling, Performance modeling, Lithographic process control

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Proceedings Article | 13 March 2018 Presentation + Paper

Approaches of multilayer overlay process control for 28nm FD-SOI derivative applications

Benjamin Duclaux, Jean De Caunes, Robin Perrier, Maxime Gatefait, Bertrand Le Gratiet, Jean-Damien Chapon, Cédric Monget

Proceedings Volume 10585, 105851C (2018) https://doi.org/10.1117/12.2292446

KEYWORDS: Overlay metrology, Optical alignment, Scanners, Process control, Data modeling, Reticles, Reliability, Optical lithography

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SPIE Journal Paper | 10 April 2015

Patterning critical dimension control for advanced logic nodes

Bertrand Le-Gratiet, Jean De-Caunes, Maxime Gatefait, Auguste Lam, Alain Ostrovsky, Jonathan Planchot, Vincent Farys, Julien Ducoté, Marc Mikolajczak, Vincent Morin, Nicolas Chojnowski, Frank Sundermann, Alice Pelletier, Regis Bouyssou, Cedric Monget, Jean-Damien Chapon, Bastien Orlando, Laurene Babaud, Céline Lapeyre, Emek Yesilada, Anna Szucs, Jean-Christophe Michel, Latifa Desvoivres, Onintza Ros Bengoechea, Pascal Gouraud

JM3, Vol. 14, Issue 02, 021103, (April 2015) https://doi.org/10.1117/12.10.1117/1.JMM.14.2.021103

KEYWORDS: Semiconducting wafers, Optical lithography, Critical dimension metrology, Process control, Photomasks, Etching, Logic, Metrology, Lithography, Optical proximity correction

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Proceedings Article | 2 April 2010 Paper

Improved CD control for 45-40 nm CMOS logic patterning: anticipation for 32-28 nm

Bertrand Le Gratiet, Frank Sundermann, Jean Massin, Marianne Decaux, Nicolas Thivolle, Fabrice Baron, Alain Ostrovsky, Cedric Monget, Jean Damien Chapon, Yoann Blancquaert, Karen Dabertrand, Lionel Thevenon, Benedicte Bry, Nicolas Cluet, Bertrand Borot, Raphael Bingert, Thierry Devoivre, Pascal Gourard, Laurène Babaud, Ute Buttgereit, Robert Birkner, Mark Joyner, Erez Graitzer, Avi Cohen

Proceedings Volume 7638, 76380A (2010) https://doi.org/10.1117/12.845987

KEYWORDS: Photomasks, Critical dimension metrology, Metrology, Etching, Scanners, Semiconducting wafers, Airborne remote sensing, Logic, Optical lithography, Process control

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Proceedings Article | 24 March 2009 Paper

Intrafield process control for 45 nm CMOS logic patterning

Bertrand Le Gratiet, Jean Massin, Alain Ostrovski, Cedric Monget, Marianne Decaux, Nicolas Thivolle, Romuald Faure, Fabrice Baron, Jean-Damien Chapon, Karen Dabertrand, Frank Sundermann, Pascal Gouraud, Laurène Babaud, Lionel Thevenon, Nicolas Cluet, Boris VandeWalle

Proceedings Volume 7272, 72722P (2009) https://doi.org/10.1117/12.812571

KEYWORDS: Reticles, Photomasks, Semiconducting wafers, Critical dimension metrology, Scanners, Metrology, Optical lithography, Process control, Scatterometry, Logic

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Proceedings Article | 22 March 2008 Paper

Process control for 45 nm CMOS logic gate patterning

Bertrand Le Gratiet, Pascal Gouraud, Enrique Aparicio, Laurene Babaud, Karen Dabertrand, Mathieu Touchet, Stephanie Kremer, Catherine Chaton, Franck Foussadier, Frank Sundermann, Jean Massin, Jean-Damien Chapon, Maxime Gatefait, Blandine Minghetti, Jean de-Caunes, Daniel Boutin

Proceedings Volume 6922, 69220Z (2008) https://doi.org/10.1117/12.776889

KEYWORDS: Semiconducting wafers, Etching, Critical dimension metrology, Optical lithography, Scatterometry, Reticles, Scanners, Photomasks, Process control, Immersion lithography

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Proceedings Article | 7 March 2008 Paper

Improving lithography intra wafer CD for C045 implant layers using STI thickness feed forward?

Jean Massin, Bastien Orlando, Maxime Gatefait, Jean-Damien Chapon, Bertrand Le-Gratiet, Blandine Minghetti, Pierre-Jérôme Goirand

Proceedings Volume 6924, 69244M (2008) https://doi.org/10.1117/12.775708

KEYWORDS: Oxides, Critical dimension metrology, Metrology, Chemical mechanical planarization, Logic, Semiconducting wafers, Etching, Optical lithography, Lithography, Scanners

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Proceedings Article | 14 May 2007 Paper

Characterization of inverse SRAF for active layer trenches on 45-nm node

Jean-Christophe Urbani, Jean-Damien Chapon, Jérôme Belledent, Amandine Borjon, Christophe Couderc, Jean-Luc Di-Maria, Vincent Farys, Franck Foussadier, Christian Gardin, Gurwan Kerrien, Laurent LeCam, Catherine Martinelli, Patrick Montgomery, Nicolo Morgana, Jonathan Planchot, Frédéric Robert, Yves Rody, Mazen Saied, Frank Sundermann, Yorick Trouiller, Florent Vautrin, Bill Wilkinson, Emek Yesilada

Proceedings Volume 6607, 66071C (2007) https://doi.org/10.1117/12.728960

KEYWORDS: SRAF, Optical proximity correction, Printing, Optical lithography, Silicon, Photomasks, Semiconducting wafers, Inspection, Optical simulations, Lithography

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Proceedings Article | 27 March 2007 Paper

ARC stack development for hyper-NA imaging

Vincent Farys, Scott Warrick, Catherine Chaton, Jean-Damien Chapon

Proceedings Volume 6520, 65204O (2007) https://doi.org/10.1117/12.712882

KEYWORDS: Reflectivity, Oxides, Chemical vapor deposition, Refractive index, Polarization, Carbon, Lithography, Multilayers, Etching, Antireflective coatings

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Proceedings Article | 15 March 2006 Paper

Immersion lithography robustness for the C065 node

Scott Warrick, Rob Morton, Andrea Mauri, Jean-Damien Chapon, Jerome Belledent, Will Conley, Alex Barr, Kevin Lucas, Cedric Monget, Valerie Plantier, David Cruau, Juan-Manuel Gomez, Emmanuel Sicurani, Jan-Willem Gemmink

Proceedings Volume 6154, 615407 (2006) https://doi.org/10.1117/12.657158

KEYWORDS: Optical proximity correction, Immersion lithography, Semiconducting wafers, Scanners, Etching, Line width roughness, Manufacturing, Optical lithography, Lithography, Metals

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Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (hp90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (hp65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).

Proceedings Article | 14 March 2006 Paper

Design and use of multivariate approach error analysis APC system

Jean de Caunes, Joost van Herk, Scott Warrick, Bertrand Le Gratiet, Marc Mikolajczak, Jean-Damien Chapon, Cedric Monget, Jan-Willem Gemmink

Proceedings Volume 6155, 615507 (2006) https://doi.org/10.1117/12.657177

KEYWORDS: Reticles, Critical dimension metrology, Semiconducting wafers, Process modeling, Overlay metrology, Oxides, Metrology, Error analysis, Semiconductors, Scanners

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Proceedings Article | 28 June 2005 Paper

Correction of long-range effects applied to the 65-nm node

Jerome Belledent, James Word, Yorick Trouiller, Christophe Couderc, Corinne Miramond, Olivier Toublan, Jean-Damien Chapon, Stanislas Baron, Amandine Borjon, Franck Foussadier, Christian Gardin, Kevin Lucas, Kyle Patterson, Yves Rody, Frank Sundermann, Jean-Christophe Urbani

Proceedings Volume 5853, (2005) https://doi.org/10.1117/12.617433

KEYWORDS: Critical dimension metrology, Etching, Photomasks, Convolution, Optical proximity correction, Electrons, Point spread functions, Optical lithography, Scattering, Light scattering

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Proceedings Article | 5 May 2005 Paper

65nm OPC and design optimization by using simple electrical transistor simulation

Yorick Trouiller, Thierry Devoivre, Jerome Belledent, Franck Foussadier, Amandine Borjon, Kyle Patterson, Kevin Lucas, Christophe Couderc, Frank Sundermann, Jean-Christophe Urbani, Stanislas Baron, Yves Rody, Jean-Damien Chapon, Franck Arnaud, Jorge Entradas

Proceedings Volume 5756, (2005) https://doi.org/10.1117/12.600887

KEYWORDS: Transistors, Ions, Optical proximity correction, Lithography, Optical lithography, Lithium, Logic, Photomasks, Lithographic illumination, Manufacturing

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Proceedings Article | 4 May 2005 Paper

Comparison between organic spin-on BARC and carbon-containing CVD stack for 65-nm gate patterning

Jean-Damien Chapon, Catherine Chaton, Pascal Gouraud, Marcel Broekaart, Scott Warrick, Isabelle Guilmeau, Yorick Trouiller, Jerome Belledent

Proceedings Volume 5753, (2005) https://doi.org/10.1117/12.601742

KEYWORDS: Chemical vapor deposition, Etching, Critical dimension metrology, Reflectivity, Carbon, Line width roughness, Semiconducting wafers, Optical lithography, Oxides, Dielectrics

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Proceedings Article | 14 May 2004 Paper

Evaluation of wet-developable KrF organic BARC to improve CD uniformity for implant application

Isabelle Guilmeau, Alice Guerrero, Vincent Blain, Stephanie Kremer, Vincent Vachellerie, Damien Lenoble, Patricia Nogueira, Sebastien Mougel, Jean-Damien Chapon

Proceedings Volume 5376, (2004) https://doi.org/10.1117/12.538061

KEYWORDS: Critical dimension metrology, Oxides, Scanning electron microscopy, Semiconducting wafers, Lithography, Optical lithography, Silicon, Scatterometry, Photoresist processing, Electroluminescence

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Proceedings Article | 26 June 2003 Paper

Gate imaging for 0.09-μm logic technology: comparison of single exposure with assist bars and the CODE approach

Yorick Trouiller, Jerome Belledent, J. D. Chapon, V. Rousset, Yves Rody, Serdar Manakli, Pierre-Jerome Goirand

Proceedings Volume 5040, (2003) https://doi.org/10.1117/12.485527

KEYWORDS: Printing, Photomasks, Lithographic illumination, Logic, Critical dimension metrology, Lithography, Optical proximity correction, Binary data, Electroluminescence, Scattering

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Proceedings Article | 30 July 2002 Paper

Complementary double-exposure technique (CODE): a way to print 80-nm gate level using a double-exposure binary mask approach

Serdar Manakli, Yorick Trouiller, Olivier Toublan, Patrick Schiavone, Corinne Miramond, Yves Rody, Frank Sundermann, J. D. Chapon, Pierre-Jerome Goirand

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474597

KEYWORDS: Photomasks, Binary data, Electroluminescence, Resolution enhancement technologies, Neodymium, Visualization, Scanners, Critical dimension metrology, Manufacturing, Printing

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Showing 5 of 17 publications

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