Derivative technology like embedded Non-Volatile Memories (eNVM) is raising new types of challenges on the “more than Moore” path. By its construction: overlay is critical across multiple layers, by its running mode: usage of high voltage are stressing leakages and breakdown, and finally with its targeted market: Automotive, Industry automation, secure transactions… which are all requesting high device reliability (typically below 1ppm level). As a consequence, overlay specifications are tights, not only between one layer and its reference, but also among the critical layers sharing the same reference. This work describes a broad picture of the key points for multilayer overlay process control in the case of a 28nm FD-SOI technology and its derivative flows. First, the alignment trees of the different flow options have been optimized using a realistic process assumptions calculation for indirect overlay. Then, in the case of a complex alignment tree involving heterogeneous scanner toolset, criticality of tool matching between reference layer and critical layers of the flow has been highlighted. Improving the APC control loops of these multilayer dependencies has been studied with simulations of feed-forward as well as implementing new rework algorithm based on multi-measures. Finally, the management of these measurement steps raises some issues for inline support and using calculations or “virtual overlay” could help to gain some tool capability. A first step towards multilayer overlay process control has been taken.
Patterning process control has undergone major evolutions over the last few years. Critical dimension, focus, and overlay control require deep insight into process-variability understanding to be properly apprehended. Process setup is a complex engineering challenge. In the era of mid k1 lithography (>0.6), process windows were quite comfortable with respect to tool capabilities, therefore, some sources of variability were, if not ignored, at least considered as negligible. The low k1 patterning (<0.4) era has broken down this concept. For the most advanced nodes, engineers need to consider such a wide set of information that holistic processing is often mentioned as the way to handle the setup of the process and its variability. The main difficulty is to break down process-variability sources in detail and be aware that what could have been formerly negligible has become a very significant contributor requiring control down to a fraction of a nanometer. The scope of this article is to highlight that today, engineers have to zoom deeper into variability. Even though process tools have greatly improved their capabilities, diminishing process windows require more than tool-intrinsic optimization. Process control and variability compensations are major contributors to success. Some examples will be used to explain how complex the situation is and how interlinked processes are today.
Since 2008, we have been presenting some papers regarding CMOS 45nm logic gate patterning activity to
reduce CD dispersion. After a global CD budget evaluation at SPIE08, we have been focusing on Intrafield CD
corrections using Dose Mapper<sup>TM</sup>. The story continues and since then we have pursued our intrafield characterisation
and focus on ways to get Dose Mapper<sup>TM</sup> dose recipe created before the first silicon is coming. In fact 40nm technology
is already more demanding and we must be ready with integrated solutions for 32/28nm node.
Global CD budget can be divided in Lot to Lot, Wafer to Wafer, Intra wafer and Intra field component. We
won't talk here about run to run solutions which are put in place for Lot to Lot and Wafer to Wafer. We will emphasize
on the intrafield / intrawafer process corrections and outline process compensation control and strategy. A lot of papers
regarding intrafield CD compensation are available in the litterature but they do not necesserally fit logic manufacturing
needs or possibilities. We need to put similar solutions in place which are comprehensive and flexible. How can we
correct upfront an Etch chamber CD profile combined with a mask and scanner CD signature? How can we get intrafield
map from random logic devices? This is what we will develop in this paper.
CMOS 45nm technology, and especially the logic gate patterning has led us to hunt for every nanometer we
could found to reach aggressive targets in term of overall CD budget. We have presented last year a paper ("Process
Control for 45 nm CMOS logic gate patterning " - B. Le Gratiet SPIE2008; 6922-33) showing the evaluation of our
process at that time. One of the key item was the intrafield control. Preliminary data were presented regarding intrafield
CD corrections using Dose Mapper<sup>TM</sup>. Since then, more work has been done in this direction and not only for the GATE
Depending on reticle specification grade, process MEEF and scanner performance, intrafield CD variation can
reach quite high CD ranges and become a non negligeable part of the overall budget. Although reticles can achieve very
good level of CD uniformity, they all have their own "footprint" which will becomes a systematic error. The key point
then is to be able to measure this footprint and correct for it on the wafer. Scanners suppliers provide tools like Dose
Mapper<sup>TM</sup> to modify the intrafield exposure dose profile. Generating and using a proper exposure "subrecipe" requires
intrafield in-line control needs on production wafers. This paper present a status of our work on this subject with some
results related to global gate CMOS 45nm CD variability improvement including etch process compensation with Dose
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
In this paper we performed an analysis of various data collection preformed on C045 production lots in order to
assess the influence of STI oxide layers on the CD uniformity of implant photolithography layers. Our final purpose is to
show whether the DOSE MAPPER<sup>TM</sup> software option for interfiled dose correction available on ASML scanners
combined with a run-to-run feed-forward regulation loop could improve global CD uniformity on C045 implants layers.
After a brief presentation of the C045 implants context the results of the analysis are presented : swing curves, process
windows analysis, and intra-die CD measurements are presented. The conclusion of the analysis is that it is not possible,
in the current C045 industrial environment, to use a robust and general method of interfield dose correction in order to
achieve a better global CD uniformity.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
The merits of hyper NA imaging using 193 nm exposure wavelength with water immersion for 45 nm and 32 nm nodes is clear. However, the challenge remains CD control at hyper NA and the development of ARC stacks to support not only lithographic response but also device integrations. Extreme off-axis illumination, polarization, and dense pitches of the C045 and C032 nodes show a significant degradation of reflection and CD control and a significant loss of resolution. Consequently, hyper NA patterning requires the development of a new ARC to improve the overall CD control. Thus, a single ARC layer could not ensure the reflectivity condition, and ARC stacks must now be decomposed into two or three components in order to suppress reflectivity through a wide range of incidence angle.
In a previous work, we presented the advantage of using an antireflective based on CVD organic - inorganic stacks. This paper presents an upgrade of this type of stack, applied to 1.2NA imaging. We will show stack reflectivity simulations based on S-matrix approach. The capabilities of the CVD tools have been taken into account in the simulations in order to define a reflectivity process window. We will present 1.2NA lithography with different optimized ARC stacks, comparing potential capability and CD control in conjunction with the immersion lithography for 45 nm and 32 nm nodes.
Semiconductor manufacturers are in the midst of the next technology node C045 (65nm half-pitch) development. The difference this time is that the heavy lifting is being done while swimming. Generally, for the C065 node (<i>hp</i>90), critical layers will be processed using 193-nm scanners with numerical apertures up to 0.85. It is also clear that the capabilities and potential benefits of immersion lithography (at this wavelength and NA) should to be examined, in addition to the development of immersion lithography for the C045 and C032 technology generations. The potential benefits of immersion lithography; increased DOF in the near term and hyper-NA imaging in the next phase, have been widely reported. A strategy of replacing conventional "dry" lithographic process steps with immersion lithographic process steps would allow the benefits of immersion to be realized much earlier. To fully realize this advantage a direct comparison of immersion lithography's benefits and therefore speed learning is needed. However, such an insertion should be "transparent": i.e. the "immersion process" should run with the same reticles (OPC) and resists, as the conventional process. In an effort to gain this knowledge about the immersion processes, we have chosen a path of optimizing and ramping-up the lithographic process for the C065 technology node. In this paper, we report on the compatibility of inserting immersion lithography processes into an established C065 process running in a pilot manufacturing line. We will present an initial assessment of some critical parameters for the implementation of immersion lithography. This assessment includes: OPC compatibility, imaging, process integration, and defectivity all compared to the dry process of record. Finally, conclusions will be made as to the overall readiness of immersion to support C065 node processing in direct transfer from dry and its extendibility to C045. In this work, the C045 technology node (<i>hp</i>65) is the main target vehicle. However, a successful introduction of immersion technology may allow a strategy change complementary with the previous (C065) technology node (i.e. run C065 immersion in production and benefit from larger process windows).
On-going complex integration schemes and developments in processes present significant challenges to lithography in manufacturing advanced semiconductor integrated circuits. Although APC solutions are in place to assist in achieving robust CD control and overlay, there is a great need to increase the 'knowledge' of the system with respect to other contributors impacting the process. The problem becomes more complex in case of an ASIC Prototyping Fab where there is no big runner concept. This leads to the need of a product effect management requirement (Product layout and reticles impact). For this reason, we developed the multivariate R2R controller. This paper discusses the multi-variant methodology and results of a new R2R regulation algorithm in a 65nm node process. Specifically, parameters such as linear combinations of terms, alignment variation for overlay modeled parameters (inter-field / intra-field), CD impacts (reticles, process, tool, STI stack etc) are studied. New solutions for future technology nodes are presented in this paper. It includes for each contributor a multivariate method to assess vector responses and noise contribution. This is being applied on CD and Overlay measurement feedback. For each source of variation (or "Contributor"), the multivariate controller provides the estimated level of compensation requested to meet the target and the level of noise induced on lot processing. At the moment the multivariate R2R controller runs in production. A real evaluation of the existing sources of variations and noise is possible and demonstrated. The result is a significant regulation performance improvement.
Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows.
For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.
In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance:
1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects.
2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples:
-design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor.
-Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.
For the past several technology nodes, switching from spin-on organic Bottom Anti-Reflective Coatings (BARCs) to CVD organic BARCs has been proposed as the optimal solution for critical photolithography processes. However, spin-on BARC film stacks have still have widespread adoption for a variety of reasons. Despite the continuous improvement in lithographic techniques, the current challenges for 65nm (half pitch) process integration demand that critical photo processes sacrifice significant pattern collapse margin to maintain high aspect ratios. In the mean time, pressure on CD control has also continued to increase. As a result of these trends, the choice and the optimization of hard mask and antireflective solutions are a critical area of process development.
This paper presents an update on the tradeoffs between spin-on organic BARCs and CVD organic integrations when applied to 65nm gate patterning constraints. The proposed Carbon containing CVD stack has shown great advantages in term of reflectivity control and in term of pattern collapse margin leading to an overall improved lithographic process window. On the other hand, satisfactory critical dimensions, without organic BARC, were seen when studying parameters such as, line width roughness (LWR), profiles and rework impact. These statements have also been assessed with some promising etch and electrical results.
As integrated circuit manufacturing moves towards smaller feature sizes, ion implant photo levels are becoming critical layers with lithography demands as tight as 180 nm line/space patterning capability. Advanced materials are required for junction levels to improve the critical dimension (CD) control and resolution. Dyed KrF resists are reaching the limit in their ability to control CD variation due to parasitic light reflections from the underlayer. The use of a bottom anti-reflective coating (BARC) under KrF resists reduces the reflective effect from the oxide substrate, leading to better CD control. Unfortunately, a standard organic BARC that requires plasma etch before implantation can cause silicon substrate oxidation damage as well as increased wafer cost due to additional process steps. The use of a new developer-soluble organic BARC shows an advantage in optics without degrading the underlying substrate before implantation. The advantage of using an ESCAP resist in combination with a wet-developable BARC over the single resist layer scheme has been clearly demonstrated and the system is well adapted to ion implant layers for 65 nm technology.
xIn order to address some specific issues related to gate level printing of the 0.09μm logic process, the following mask and illumination solutions have been evaluated. Annular and Quasar illumination using binary mask with assist feature and the CODE (Complementary Double Exposure) technique. Two different linewidths have been targeted after lithography: 100nm and 80nm respectively for lowpower and high-speed applications. The different solutions have been compared for their printing performance through pitch for Energy Latitude, Depth of Focus and Mask Error Enhancement Factor. The assist bar printability and line-end control was also determined. For printing the 100nm target, all tested options can be used, with a preference for Quasar illumination for the gain in Depth of Focus and
MEEF. For the 80nm target however, only the CODE technique with Quasar give sufficient good results for the critical litho parameters.
To follow the accelerating ITRS roadmap, microprocessor and DRAM manufacturers have introduced the Alternating Phase shift mask (Alt.PSM) resolution enhancement technique (RET) in order to be able to print the gate level on sub 130nm devices. This is done at very high mask costs, a long cycle time and poor guarantee to get defect free masks. S. Nakao has proposed a new RET. He showed that sub 0.1um features could be printed with good process latitudes using a double binary mask printing technique. This solution is very interesting, but is applicable to isolated structures only. To overcome this limitation, we have developed an extension to this technique called CODE. This combines Nakao's technique and the use of assist features removed in a second subsequent exposure. This new solution enables us to print isolated as well as dense features on advanced devices using two binary masks. This paper will describe all the steps required to develop the CODE application. (1) Determination of the optimal optical settings, (2) Determination of optimal assist feature size and placement, (3) Layout rules generation, (4)Application of the layout rules to a complex layout, using the Mentor Graphics Calibre environment, (5) Experimental verification using a 193nm 0.63NA scanner.