Mr. Jean-Marie Brunet Profile

Jean-Marie Brunet

Market Development Manager at Siemens EDA

SPIE Involvement:

Author

Publications (6)

Proceedings Article | 18 March 2015 Paper

High coverage of litho hotspot detection by weak pattern scoring

Jinho Park, NamJae Kim, Jae-hyun Kang, Seung Weon Paek, Steve Kwon, Marwah Shafee, Kareem Madkour, Wael ElManhawy, Joe Kwan, Jean-Marie Brunet

Proceedings Volume 9427, 942703 (2015) https://doi.org/10.1117/12.2087473

KEYWORDS: Phase modulation, Lithography, Image classification, Library classification systems, Visualization, Process modeling, Design for manufacturing, Manufacturing, Yield improvement, Land mines

Read Abstract +

Achieving lithographic printability at advanced nodes (14nm and beyond) can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. Early identifying of yield-limiter hotspots is essential for both foundries and designers to significantly improve process maturity. A real challenge is to scan the design space to identify hotspots, and decide the proper course of action regarding each hotspot. Building a scored pattern library with real candidates for hotspots for both foundries and designers is of great value. Foundries are looking for the most used patterns to optimize their technology for and identify patterns that should be forbidden, while designers are looking for the patterns that are sensitive to their neighboring context to perform lithographic simulation with their context to decide if they are hotspots or not.[1] In this paper we propose a framework to data mine designs to obtain set of representative patterns of each design, our aim is to sample the designs at locations that can be potential yield limiting. Though our aim is to keep the total number of patterns as small as possible to limit the complexity, still the designer is free to generate layouts results in several million of patterns that define the whole design space. In order to handle the large number of patterns that represent the design building block constructs, we need to prioritize the patterns according to their importance. The proposed pattern classification methodology depends on giving scores to each pattern according to the severity of hotspots they cause, the probability of their presence in the design and the likelihood of causing a hotspot. The paper also shows how the scoring scheme helps foundries to optimize their master pattern libraries and priorities their efforts in 14nm technology and beyond. Moreover, the paper demonstrates how the hotspot scoring helps in improving the runtime of lithographic simulation verification by identifying which patterns need to be optimized to correctly describe candidate hotspots, so that only potential problematic patterns are simulated.

Proceedings Article | 28 March 2014 Paper

Model based multilayers fix for litho hotspots beyond 20nm node

Asmaa Rabie, Kareem Madkour, Kirolos George, Wael ElManhawy, Jean-Marie Brunet, Joe Kwan

Proceedings Volume 9053, 90530F (2014) https://doi.org/10.1117/12.2045744

KEYWORDS: Double patterning technology, Metals, Photomasks, Lithography, Manufacturing, Visualization, Design for manufacturing, Multilayers, Bridges, Standards development

Read Abstract +

Proceedings Article | 29 March 2013 Paper

Model based hint for litho hotspot fixing beyond 20nm node

Jae-Hyun Kang, Byung-Moo Kim, Naya Ha, Hung bok Choi , Kee sup Kim , Sarah Mohamed, Kareem Madkour, Wael ElManhawy, Evan Lee, Jean-Marie Brunet, Joe Kwan

Proceedings Volume 8684, 86840N (2013) https://doi.org/10.1117/12.2011619

KEYWORDS: Lithography, Double patterning technology, Design for manufacturing, Resolution enhancement technologies, Manufacturing, Bridges, Visualization, Design for manufacturability, Metals, Electronics

Read Abstract +

Proceedings Article | 4 March 2008 Paper

System to improve RET-OPC production by dynamic design coverage using sign-off litho simulator

Mark Simmons, Jean-Marie Brunet, Seung-Weon Paek, Y. K. Kim

Proceedings Volume 6925, 69250X (2008) https://doi.org/10.1117/12.771821

KEYWORDS: Optical proximity correction, Product engineering, Process modeling, Computer aided design, Resolution enhancement technologies, Semiconducting wafers, Data modeling, Manufacturing, Error analysis, Calibration

Read Abstract +

Proceedings Article | 21 March 2007 Paper

Litho aware method for circuit timing/power analysis through process

R. Fathy, M. Al-Imam, H. Diab, M. Fakhry, J. A. Torres, B. Graupp, J. M. Brunet, M. Bahnas

Proceedings Volume 6521, 65210O (2007) https://doi.org/10.1117/12.711723

KEYWORDS: Lithography, Oscillators, Semiconducting wafers, Transistors, Visualization, Design for manufacturing, Integrated circuit design, Silicon, Process modeling, Etching

Read Abstract +

Proceedings Article | 20 October 2006 Paper

Optimization of process window simulations for litho-friendly design framework

Mohamed Al-Imam, Andres Torres, Jean-Marie Brunet, Moutaz Fakhry, Rami Fathy

Proceedings Volume 6349, 63491C (2006) https://doi.org/10.1117/12.686313

KEYWORDS: Lithography, Image processing, Standards development, Photovoltaics, Capacitors, Visualization, Manufacturing, Silicon, Semiconducting wafers, Design for manufacturing

Read Abstract +

Showing 5 of 6 publications

View contact details

UPDATE YOUR PROFILE

Is this your profile? Update it now.

Sign into your SPIE.org account

Don’t have a profile and want one?

Create an account on SPIE.org

Keywords/Phrases

Search In:

Publication Years