Achieving lithographic printability at advanced nodes (14nm and beyond) can impose significant restrictions on physical design, including large numbers of complex design rule checks (DRC) and compute-intensive detailed process model checking. Early identifying of yield-limiter hotspots is essential for both foundries and designers to significantly improve process maturity. A real challenge is to scan the design space to identify hotspots, and decide the proper course of action regarding each hotspot. Building a scored pattern library with real candidates for hotspots for both foundries and designers is of great value. Foundries are looking for the most used patterns to optimize their technology for and identify patterns that should be forbidden, while designers are looking for the patterns that are sensitive to their neighboring context to perform lithographic simulation with their context to decide if they are hotspots or not. In this paper we propose a framework to data mine designs to obtain set of representative patterns of each design, our aim is to sample the designs at locations that can be potential yield limiting. Though our aim is to keep the total number of patterns as small as possible to limit the complexity, still the designer is free to generate layouts results in several million of patterns that define the whole design space. In order to handle the large number of patterns that represent the design building block constructs, we need to prioritize the patterns according to their importance. The proposed pattern classification methodology depends on giving scores to each pattern according to the severity of hotspots they cause, the probability of their presence in the design and the likelihood of causing a hotspot. The paper also shows how the scoring scheme helps foundries to optimize their master pattern libraries and priorities their efforts in 14nm technology and beyond. Moreover, the paper demonstrates how the hotspot scoring helps in improving the runtime of lithographic simulation verification by identifying which patterns need to be optimized to correctly describe candidate hotspots, so that only potential problematic patterns are simulated.
Sub-20nm node designs are getting more sophisticated, and printability issues become more critical which need more advanced techniques to fix. It is mandatory for designers to run lithography checks before tapeout, and it is very challenging to fix all of the generated hotspots manually without introducing unintentional hotspots, or DPT violations. This paper presents a methodology for fixing hotspots on DPT layouts, using the same Model Based Hints (MBH) engine used for detecting hotspots. The fix is based on DRC and DPT constrained minimum movement of edges causing the hotspot, which guarantees that the fix does not violate any of the specified DRC or DPT constraints, nor does it need recoloring. The fix is extended along multilayers to fulfill the specified DRC and DPT constraints and guarantees circuit connectivity along the layers stack. This multilayers approach fixes hotspots that were impossible to fix previously. This methodology is demonstrated on industrial designs, where real hotspots were fixed and the fixing rate is reported.
As technology nodes scale beyond 20nm node, design complexity increases and printability issues become more critical and hard for RET techniques to fix. It is now mandatory for designers to run lithography checks prior to tape out and acceptance by the foundry. As lithography compliance became a sign-off criterion, lithography hotspots are increasingly treated like DRC violations. In the case of lithography hotspot, layout edges that should be moved to fix the hotspot are not necessarily the edges directly touching it. As a result of that, providing the designer with a suggested layout movements to fix the lithography hotspot is becoming a necessity. Software solutions generating hints should be accurate and fast. In this paper we are presenting a methodology for providing hints to the designers to fix Litho-hotspots in the 20nm and beyond.
The advanced process technologies have well known yield loss due to the degradation of pattern fidelity. The
process to compensate for this problem is advanced resolution enhancement techniques (RET) and optical proximity
correction (OPC). By design, the creation of RET/OPC recipes and the calibration of process models are done very early
in the process development cycle with data that are not made of real designs since they are not yet available, but made of
test structures that represent different sizes, distances and topologies. The process of improving the RET/OPC recipes
and models is long and tedious, it is usually a key contributor to quick production ramp-up. It is very coverage limited
by design. The authors will present a proposed system that, by design, is dynamic, and allows the RET/OPC production
system to reach maturity faster through a detailed collection of hotspots identified at the design stage. The goal is to
reduce the lapse of time required to get mature production RET/OPC recipes and models.
Device extraction and the quality of device extraction is becoming of increasing concern for integrated
circuit design flow. As circuits become more complicated with concomitant reductions in geometry, the
design engineer faces the ever burgeoning demand of accurate device extraction. For technology nodes of
65nm and below approximation of extracting the device geometry drawn in the design layout
polygons might not be sufficient to describe the actual electrical behavior for these devices, therefore
contours from lithographic simulations need to be considered for more accurate results.
Process window variations have a considerable effect on the shape of the device wafer contour, having an
accurate method to extract device parameters from wafer contours would still need to know which
lithographic condition to simulate. Many questions can be raised here like: Are contours that represent the
best lithography conditions just enough? Is there a need to consider also process variations? How do we
include them in the extraction algorithm?
In this paper we first present the method of extracting the devices from layout coupled with lithographic simulations. Afterwards a complete flow for circuit time/power analysis using lithographic contours is described. Comparisons between timing results from the conventional LVS method and Litho aware method are done to show the importance of litho contours considerations.
Cutting edge technology node manufacturers are always researching how to increase yield while still optimally using
silicon wafer area, this way these technologies will appeal more to designers. Many problems arise with such
requirements, most important is the failure of plain layout geometric checks to capture yield limiting features in designs,
if these features are recognized at an early stage of design, it can save a lot of efforts at the fabrication end. A new trend
of verification is to couple geometric checks with lithography simulations at the designer space.
A lithography process has critical parameters that control the quality of its resulting output. Unfortunately some of these
parameters can not be kept constant during the exposure process, and the variability of these parameters should be taken
into consideration during the lithography simulations, and the lithography simulations are performed multiple times with
these variables set at the different values they can have during the actual process. This significantly affects the runtime
In this paper the authors are presenting a methodology to carefully select only needed values for varying lithography
parameters; that would capture the process variations and improve runtime due to reduced simulations. The selected
values depend on the desired variation for each parameter considered in the simulations. The method is implemented as
a tool for qualification of different design techniques.