Along with process improvement and integrated circuit (IC) design complexity increased, failure rate caused by optical getting higher in the semiconductor manufacture. In order to enhance chip quality, optical proximity correction (OPC) plays an indispensable rule in the manufacture industry. However, OPC, includes model creation, correction, simulation and verification, is a bottleneck from design to manufacture due to the multiple iterations and advanced physical behavior description in math. Thus, this paper presented a pattern-based design technology co-optimization (PB-DTCO) flow in cooperation with OPC to find out patterns which will negatively affect the yield and fixed it automatically in advance to reduce the run-time in OPC operation.
PB-DTCO flow can generate plenty of test patterns for model creation and yield gaining, classify candidate patterns systematically and furthermore build up bank includes pairs of match and optimization patterns quickly. Those banks can be used for hotspot fixing, layout optimization and also be referenced for the next technology node. Therefore, the combination of PB-DTCO flow with OPC not only benefits for reducing the time-to-market but also flexible and can be easily adapted to diversity OPC flow.
Beyond 40nm lithography node, mask topograpy is important in litho process. The rigorous EMF simulation should
be applied but cost huge time. In this work, we compared experiment data with aerial images of thin and thick mask
models to find patterns which are sensitive to mask topological effects and need rigorous EMF simulations. Furthur more,
full physical and simplified lumped (LPM) resist models were calibrated for both 2D and 3D mask models. The accuracy
of CD prediction and run-time are listed to gauge the most efficient simulation. Although a full physical resist model
mimics the behavior of a resist material with rigor, the required iterative calculations can result in an excessive execution
time penalty, even when simulating a simple pattern. Simplified resist models provide a compromise between
computational speed and accuracy.
The most efficient simulation approach (i.e. accurate prediction of wafer results with minimum execution time) will
have an important position in mask 3D simulation.