A dual damascene template fabrication process has been developed, which enables the structuring of high-resolution,
high-aspect pillars on top of lines. Based on this technology templates with three different designs have been fabricated
and characterized. Two templates are dedicated for an assessment of the fabrication process using a regular test design
on one hand and an arbitrary CMOS design on the other hand. With the third template via chains shall be later realized as
demonstrator for electrical tests. The templates have been imprinted in resist and sacrificial material on an Imprio 55 and
an Imprio 100 tool. The usability of each fabricated template could be confirmed for the specific application. For the
template manufacturing a Vistec variable shape e-beam (VSB) writer SB352HR and appropriate positive-tone and
negative-tone chemically amplified resists (CAR) have been used.
Step and Flash Imprint Lithography (S-FIL®) in conjunction with Sacrificial Imprint Materials (SIM)
shows promise as a cost effective solution to patterning sub 45nm features and is capable of
simultaneously patterning two levels of interconnect structures, which provides a high throughput
and low cost BEOL process. This paper describes the integration of S-FIL into an industry
standard Cu/low-k dual damascene process that is being practiced in the ATDF at Sematech in
Austin. The pattern transferring reactive ion etching (RIE) process is the most critical step and
was extensively explored in this study. In addition to successful process development, the results
provide useful insight into the optimal design of multilevel templates which must take into account
the characteristics of both the imaging material and the dielectric layer.
The template used in this study incorporates both the via and trench levels of an M2 (Metal 2) test
vehicle that incorporates via chains with varying via dimensions, Kelvin test structures,
serpentines, etc. The smallest vias on the template are 120nm vias with an aspect ratio of 2.0
and the smallest dense lines are 125nm/175nm with an aspect ratio of 2.9. Two inter-level
dielectrics (ILD), Coral® and Black Diamond® were studied. No trench etch stop was incorporated
in the ILD film stack. A multi-step, in-situ etching scheme was developed that achieves faithful
pattern transfer from the sacrificial imprint material (SIM) into the underlying low k ILD with
surprisingly wide process latitude. This multi-step scheme includes the following etch steps: a
residual layer open, a via etch, a trench descum, a trench etch, and an SIM removal ash. Among
these steps, the trench etch was found to be the most challenging to develop and it holds the key
to producing high aspect ratio dual damascene features. An etching chemistry based on two
fluorocarbon gases, CF4 and C4F8, was found to be very effective in delivering the desired etch
profiles with optimal sidewall angle, minimal facet formation. The optimized etch process can be
exploited to provide substantial size reduction and/or increased aspect ratio relative to the
template. In this way structures with final critical dimensions of 95nm in vias with aspect ratio of
3.0 and 67nm/233nm in dense lines with aspect ratio of 3.6 were demonstrated with wide process
latitude. This enables manufacturing of the template at larger dimensions, which simplifies both
fabrication and inspection.
The successful development of the dual damascene RIE process at the second metal (M2) level
was demonstrated in a mixed and matched build with an ATDF standard first layer metal (M1)
process. The M1 dielectric was TEOS and was patterned by 248nm lithography. The M2 and Via
levels used Coral as ILD and both levels were patterned simultaneously by S-FIL using Molecular
Imprint Imprio 55 and Imprio 100 imprint tools. This electrical test vehicle provided solid evidence
that S-FIL is fully compatible with industry standard dual damascene process.
The dual damascene process used to generate copper interconnects requires many difficult processing steps. Back End Of Line (BEOL) processing using Step and Flash Imprint Lithography (SFIL) on a directly patternable dielectric material can dramatically reduce the number of processing steps. By using multi-level SFIL rather than photolithography, two levels of interconnect structure (trench and corresponding via) can be patterned simultaneously. In addition, the imprinted material can be a imprintable dielectric precursor rather than a resist, further reducing the total number of steps in the dual damascene process. This paper presents progress towards integrating multi-level SFIL into a copper CMP process flow at ATDF, Inc. in Austin, Texas. Until now, work has focused on multi-level imprint process development. This report focuses on the development of new imprintable dielectric precursors for use with the dual damascene imprint process. SFIL compatible dielectric precursors were synthesized and characterized for integration into the ATDF copper CMP process flow. SFIL requires properties not found in currently available semiconductor dielectrics such as low viscosity and rapid photo-induced polymerization. Inorganic/organic hybrid materials derived from sol-gel chemistry and polyhedral oligomeric silsesquioxane (POSS) structures show promise for this application. The properties of three different dielectric layers are compared. The viability of each material as an interlayer dielectric is discussed and the results of multi-level patterning, metal fill, and polish are shown.
Advanced microprocessors require several (eight or more) levels of wiring to carry signal and power from transistor to transistor and to the outside world. Each wiring level must make connection to the levels above and below it through via/contact layers. The dual damascene approach to fabricating these interconnected structures creates a wiring level and a via level simultaneously, thereby reducing the total number of processing steps. However, the dual damascene strategy (of which there are several variations) still requires around twenty process steps per wiring layer. In this work, an approach to damascene processing that is based on step-and-flash imprint lithography (SFIL) is discussed. This imprint damascene process requires fewer than half as many steps as the standard photolithographic dual damascene approach. By using an imprint template with two levels of patterning, a single imprint lithography step can replace two photolithography steps. Further efficiencies are possible if the imprint resist material is itself a functional dielectric material. This work is a demonstration of the compatibility of imprint lithography (specifically SFIL) with back-end-of-line processing using a dual damascene approach with functional materials.