Mr. Jeffrey P. Mayhew Profile

Jeffrey P. Mayhew

Senior Manager of R&D at Synopsys Inc

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Publications (11)

Proceedings Article | 17 October 2008 Paper

Model-based assist feature placement: an inverse imaging approach

Amyn Poonawala, Benjamin Painter, Jeffrey Mayhew

Proceedings Volume 7122, 71220U (2008) https://doi.org/10.1117/12.801539

KEYWORDS: Atrial fibrillation, Photomasks, Model-based design, Inverse problems, Lithography, Optimization (mathematics), Optical lithography, Phase shifts, Detection and tracking algorithms, Inverse imaging problems

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Proceedings Article | 31 October 2007 Paper

Improvements in model-based assist feature placement algorithms

Benjamin Painter, Levi Barnes, Jeffrey Mayhew, Yongdong Wang

Proceedings Volume 6730, 67304Y (2007) https://doi.org/10.1117/12.746702

KEYWORDS: Model-based design, Atrial fibrillation, Optical proximity correction, Systems modeling, Image processing, Photomasks, Process modeling, System on a chip, Optical components, Image resolution

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Proceedings Article | 15 May 2007 Paper

Functionality and performance improvements with field-based OPC

Ben Painter, Kunal Taravade, Levi Barnes, Robert Lugg, Jeff Mayhew, Glenn Newell, Kevin Lucas

Proceedings Volume 6607, 66072T (2007) https://doi.org/10.1117/12.729012

KEYWORDS: Optical proximity correction, Model-based design, Resolution enhancement technologies, Atrial fibrillation, Image segmentation, Semiconducting wafers, Lithography, Tolerancing, Performance modeling, Computer simulations

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Proceedings Article | 21 June 2006 Paper

Assist feature placement analysis using focus sensitivity models

Lawrence Melvin, Jeffrey Mayhew, Benjamin Painter, Levi Barnes

Proceedings Volume 6281, 62810X (2006) https://doi.org/10.1117/12.692745

KEYWORDS: SRAF, Manufacturing, Process modeling, Performance modeling, Optical lithography, Semiconducting wafers, Image processing, Photomasks, Photoresist materials, Image segmentation

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Proceedings Article | 3 May 2004 Paper

Hybrid AAPSM compliance methodology to ensure design for manufacturing

Vishnu Kamat, Alexander Miloslavsky, Vinod Malhotra, Jeffrey Mayhew, Michel Cote

Proceedings Volume 5379, (2004) https://doi.org/10.1117/12.561828

KEYWORDS: Photomasks, Phase shifts, Lithography, Resolution enhancement technologies, Manufacturing, Transistors, Semiconductors, Optical proximity correction, Design for manufacturing, 193nm lithography

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Proceedings Article | 28 August 2003 Paper

Anticipating and controlling mask costs within EDA physical design

Michael Rieger, Jeffrey Mayhew, Lawrence Melvin, Robert Lugg, Daniel Beale

Proceedings Volume 5130, (2003) https://doi.org/10.1117/12.504270

KEYWORDS: Photomasks, Optical proximity correction, Tolerancing, Silicon, Semiconducting wafers, Lithography, Vestigial sideband modulation, Inspection, Model-based design, Electronic design automation

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For low k1 lithography, more aggressive OPC is being applied to critical layers, and the number of mask layers with OPC treatments is growing rapidly. The 130 nm, process node required, on average, 8 layers containing rules- or model-based OPC. The 90 nm node will have 16 OPC layers, of which 14 layers contain aggressive model-based OPC. This escalation of mask pattern complexity, coupled with the predominant use of vector-scan e-beam (VSB) mask writers contributes to the rising costs of advanced mask sets. Writing times for OPC layouts are several times longer than for traditional layouts, making mask exposure the single largest cost component for OPC masks. Lower mask yields, another key factor in higher mask costs, is also aggravated by OPC. Historical mask set costs are plotted below. The initial cost of a 90 nm-node mask set will exceed one million dollars. The relative impact of mask cost on chip depends on how many total wafers are printed with each mask set. For many foundry chips, where unit production is often well below 1000 wafers, mask costs are larger than wafer processing costs. Further increases in NRE may begin to discourage these suppliers' adoption to 90 nm and smaller nodes. In this paper we will outline several alternatives for reducing mask costs by strategically leveraging dimensional margins. Dimensional specifications for a particular masking layer usually are applied uniformly to all features on that layer. As a practical matter, accuracy requirements on different features in the design may vary widely. Take a polysilicon layer, for example: global tolerance specifications for that layer are driven by the transistor-gate requirements; but these parameters over-specify interconnect feature requirements. By identifying features where dimensional accuracy requirements can be reduced, additional margin can be leveraged to reduce OPC complexity. Mask writing time on VSB tools will drop in nearly direct proportion to reduce shot count. By inspecting masks with reference to feature-dependent margins, instead of uniform specifications, mask yield can be effectively increased further reducing delivered mask expense.

Proceedings Article | 27 December 2002 Paper

Programmable RET mask layout verification

Daniel Beale, Jeffrey Mayhew, Michael Rieger, Zongwu Tang

Proceedings Volume 4889, (2002) https://doi.org/10.1117/12.471299

KEYWORDS: Photomasks, Resolution enhancement technologies, Optical proximity correction, Tolerancing, Lithography, Silicon, Semiconducting wafers, Model-based design, Manufacturing, Bridges

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Proceedings Article | 1 August 2002 Paper

Enriching design intent for optimal OPC and RET

Michael Rieger, Valery Gravoulet, Jeffrey Mayhew, Daniel Beale, Robert Lugg

Proceedings Volume 4754, (2002) https://doi.org/10.1117/12.476939

KEYWORDS: Optical proximity correction, Photomasks, Silicon, Tolerancing, Resolution enhancement technologies, Transistors, Model-based design, Lithography, Manufacturing, Integrated circuit design

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Proceedings Article | 12 July 2002 Paper

Verifying RET mask layouts

Jeffrey Mayhew, Michael Rieger, Jiangwei Li, Lin Zhang, Zongwu Tang, James Shiely

Proceedings Volume 4692, (2002) https://doi.org/10.1117/12.475670

KEYWORDS: Resolution enhancement technologies, Photomasks, Tolerancing, Optical proximity correction, Semiconducting wafers, Process modeling, Lithography, Model-based design, Metals, Manufacturing

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Proceedings Article | 11 March 2002 Paper

OPC strategies to minimize mask cost and writing time

Michael Rieger, Jeffrey Mayhew, Jiangwei Li, James Shiely

Proceedings Volume 4562, (2002) https://doi.org/10.1117/12.458287

KEYWORDS: Optical proximity correction, Tolerancing, Photomasks, Semiconducting wafers, Databases, Prototyping, Manufacturing, Lithography, Mask making, Model-based design

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Proceedings Article | 5 July 2000 Paper

Understanding the parameters for strong phase-shift mask lithography

Alexander Tritchkov, John Stirniman, Jeffrey Mayhew, Michael Rieger

Proceedings Volume 4000, (2000) https://doi.org/10.1117/12.388970

KEYWORDS: Photomasks, Semiconducting wafers, Lithography, Optical proximity correction, Critical dimension metrology, Manufacturing, Binary data, Phase shifts, Error analysis, Systems modeling

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Showing 5 of 11 publications

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