In this paper, we study the problem of placement-level layout optimization for designs built from cells with unidirectional
self-aligned double patterning (SADP) metal-1 interconnect. Our goal is to minimize the number of potential
bridging hotspots in design layouts using predictive, machine learning-based models and applying incremental
placement adjustments. In the first part of the paper, we explain how to build layout pattern classification models using
machine learning methods. Our support vector machine (SVM)-based model predicts a given layout clip as either robust
or non-robust. In the second part of the paper, we apply the predictive models to placement-level optimization. Our
algorithm identifies and eliminates potential hotspots in standard cell based layout by modifying local cell position.
Early lithographic hotspot detection has become increasingly important in achieving lithography-friendly designs and
manufacturability closure. Fast physical verification tools employing pattern matching or machine learning techniques
have emerged as great options for detecting hotspots in the early design stages. In this work, we propose a
characterization methodology that provides measurable quantification of a given hotspot detection tool's capability to
capture a previously seen or unseen hotspot pattern. Using this methodology, we conduct a side-by-side comparison of
two hotspot detection methods-one using pattern matching and the other based on machine learning. The experimental
results reveal that machine learning classifiers are capable of predicting unseen samples but may mispredict some of its
training samples. On the other hand, pattern matching-based tools exhibit poorer predictive capability but guarantee full
and fast detection on all their training samples. Based on these observations, we propose a hybrid detection solution that
utilizes both pattern matching and machine learning techniques. Experimental results show that the hybrid solution
combines the strengths of both algorithms and delivers improved detection accuracy while sacrificing little runtime
Advances in lithography patterning have been the primary driving force in microelectronics manufacturing processes.
With the increasing gap between the wavelength of the optical source and feature sizes, the accompanying strong
diffraction effects have a significant impact on the pattern fidelity of on-silicon layout shapes. Layout patterns become
highly sensitive to those context shapes lying within the optical radius of influence. Under such optical proximity effects,
manufacturability hot spots such as necking and bridging may occur. Studies have shown that manufacturability hot
spots are pattern dependent in nature and should be considered at the design stage . It is desirable to detect these hot
spots as early as possible in the design flow to minimize the costs for correction.
In this work, we propose a hot spot prediction method based on a support vector machine technique. Given the location
of a hot spot candidate and its context patterns, the proposed method is capable of efficiently predicting whether a
candidate would become a hot spot. It takes just seconds to classify thousands of samples. Due to its computational
efficiency, it is possible to use this method in physical design tools to rapidly assess the quality of printed patterns. We
demonstrate one such application in which we evaluate the layout quality in the boundary region of standard cells. In the
conventional standard cell layout optimization process, lithography simulation is the main layout verification method.
Since it is a very time-consuming process, the iterative optimization approach between simulation and layout correction
 takes a long time and only a limited number of context patterns can be explored. We show that with the proposed hot
spot prediction method, for each standard cell, a much greater context pattern space can be explored, and the context
sensitivity of a hot spot candidate located near a cell boundary can be estimated.
As CMOS feature size scales down to 65nm and below, challenges for device and circuit manufacturability are
emerging. As commonly seen in real designs, devices with distorted gate shapes and rough line-edges are manufactured
despite the applications of aggressive resolution enhancement techniques (RET). It has been shown that such irregular
gates could introduce significant extra leakage current. Existing tools and device models cannot handle non-rectangular
geometries. Therefore, it is critical that a modeling flow capable of handling such irregular devices is developed and
smoothly integrated into the post-lithography delay and leakage circuit analysis process. Previously proposed methods
either model an irregular transistor as two different rectangular devices, one for on and the other for off state analyses; or
they are difficult to be implemented. In this paper, we propose a new modeling approach that serves as a fast and simple
solution to this problem and overcomes these drawbacks. We found that by adjusting both gate length and width of the
equivalent device, a single equivalent rectangular device can be determined. Through TCAD and SPICE simulation
experiments, we demonstrate that our model can accurately capture both on and off currents of the modeled nonrectangular
gate device. The average error of our modeling approach is 1.6% for I<sub>on</sub> and 7.5% for I<sub>off</sub>.