Despite the innumerable advances in EUV lithography for materials, optics, and process in recent years, the N7 and N5 targets for resolution, line roughness, and sensitivity (RLS, collectively) have not simultaneously been achieved from both a yield and cost perspective due to their interdependent nature. For example, reducing dose to an economically practical level results in resolution and roughness levels that generate unacceptable yield and performance. These limitations have traditionally been viewed in a light where only conventional post-lithographic processing by etch is used for the subsequent pattern transfer. Recent post-lithography defect mitigation techniques, however, combine the use of high etch selectivity underlayers, atomic layer etch (ALE) descum, and fast-switching deposition and etch resist linespace pattern repair have overcome the limitations of the RLS interdependency by correcting for resolution and stochastics related defects and improving LER associated with lower exposure dose . Here, an aspect ratio dependent deposition can be used to protect the resist lines from further notching and damage while allowing for residual scum between the lines to be etched . A lithography, etch, and metrology feedback loop can be envisioned in which a minimum dose requirement is found where both the LER and lithography related defects are still correctable using post-exposure processing; however, due to the extremely long metrology times for e-beam inspection combined with the large quantity of adjustable parameters, traditional experimental DOEs quickly become unmanageable. The intractability of this situation necessitates a simulation-based parameter space optimization to reduce the required number of feedback cycles. In this study, Coventor SEMulator3D® is used to find optimized solutions for minimizing resist line bridges and breaks as well as line smoothing. Here, distributions of line roughness and resist divot and scum dimensions can be subjected to simulated process recipes with tunable parameters like etch selectivities, aspect ratio dependence of deposition and etch, deposition and etch rates, number of ALE cycles, etc. that one would typically explore in this defect mitigation strategy. The resulting defects can then be analyzed to determine how each defect in the distribution reacts to a given treatment. Additionally, further insight can be gleaned regarding the types and dimensions of defects that can be corrected and that would otherwise not be measurable using any physical metrology. For example, at low dose, a portion of the defect size distribution is comparable to the drawn features and can no longer be corrected by the post-exposure treatment. Due to the randomness of the defects and small size, three-dimensional characterization is difficult, but using simulation, it is possible to show at what dimension the defect mitigation strategy begins to fail.
Edge placement error (EPE) has become an increasingly critical metric to enable Moore’s Law scaling. Stochastic variations, as characterized for lines by line width roughness (LWR) and line edge roughness (LER), are dominant factors in EPE and known to increase with the introduction of EUV lithography. However, despite recommendations from ITRS, NIST, and SEMI standards, the industry has not agreed upon a methodology to quantify these properties. Thus, differing methodologies applied to the same image often result in different roughness measurements and conclusions. To standardize LWR and LER measurements, Fractilia has developed an unbiased measurement that uses a raw unfiltered line scan to subtract out image noise and distortions. By using Fractilia’s inverse linescan model (FILM) to guide development, we will highlight the key influences of roughness metrology on plasma-based resist smoothing processes. Test wafers were deposited to represent a 5 nm node EUV logic stack. The patterning stack consists of a core Si target layer with spin-on carbon (SOC) as the hardmask and spin-on glass (SOG) as the cap. Next, these wafers were exposed through an ASML NXE 3350B EUV scanner with an advanced chemically amplified resist (CAR). Afterwards, these wafers were etched through a variety of plasma-based resist smoothing techniques using a Lam Kiyo conductor etch system. Dense line and space patterns on the etched samples were imaged through advanced Hitachi CDSEMs and the LER and LWR were measured through both Fractilia and an industry standard roughness measurement software. By employing Fractilia to guide plasma-based etch development, we demonstrate that Fractilia produces accurate roughness measurements on resist in contrast to an industry standard measurement software. These results highlight the importance of subtracting out SEM image noise to obtain quicker developmental cycle times and lower target layer roughness.
Extreme ultraviolet (EUV) lithography is crucial to enabling technology scaling in pitch and critical dimension (CD). Currently, one of the key challenges of introducing EUV lithography to high volume manufacturing (HVM) is throughput, which requires high source power and high sensitivity chemically amplified photoresists. Important limiters of high sensitivity chemically amplified resists (CAR) are the effects of photon shot noise and resist blur on the number of photons received and of photoacids generated per feature, especially at the pitches required for 7 nm and 5 nm advanced technology nodes. These stochastic effects are reflected in via structures as hole-to-hole CD variation or local CD uniformity (LCDU). Here, we demonstrate a synergy of film stack deposition, EUV lithography, and plasma etch techniques to improve LCDU, which allows the use of high sensitivity resists required for the introduction of EUV HVM. Thus, to improve LCDU to a level required by 5 nm node and beyond, film stack deposition, EUV lithography, and plasma etch processes were combined and co-optimized to enhance LCDU reduction from synergies.
Test wafers were created by depositing a pattern transfer stack on a substrate representative of a 5 nm node target layer. The pattern transfer stack consisted of an atomically smooth adhesion layer and two hardmasks and was deposited using the Lam VECTOR PECVD product family. These layers were designed to mitigate hole roughness, absorb out-of-band radiation, and provide additional outlets for etch to improve LCDU and control hole CD. These wafers were then exposed through an ASML NXE3350B EUV scanner using a variety of advanced positive tone EUV CAR. They were finally etched to the target substrate using Lam Flex dielectric etch and Kiyo conductor etch systems. Metrology methodologies to assess dimensional metrics as well as chip performance and defectivity were investigated to enable repeatable patterning process development.
Illumination conditions in EUV lithography were optimized to improve normalized image log slope (NILS), which is expected to reduce shot noise related effects. It can be seen that the EUV imaging contrast improvement can further reduce post-develop LCDU from 4.1 nm to 3.9 nm and from 2.8 nm to 2.6 nm. In parallel, etch processes were developed to further reduce LCDU, to control CD, and to transfer these improvements into the final target substrate. We also demonstrate that increasing post-develop CD through dose adjustment can enhance the LCDU reduction from etch. Similar trends were also observed in different pitches down to 40 nm. The solutions demonstrated here are critical to the introduction of EUV lithography in high volume manufacturing. It can be seen that through a synergistic deposition, lithography, and etch optimization, LCDU at a 40 nm pitch can be improved to 1.6 nm (3-sigma) in a target oxide layer and to 1.4 nm (3-sigma) at the photoresist layer.