In recent year, the thermal effect has become a critical issue on the operation of memory cell. As heating time or temperature increases, the performances of memory cells are degraded due to its low thermal stabilities. Therefore, processes working at low temperature are necessary not to hurt the thermal stability. In this paper, we introduced LTSOC (Low Temperature Spin-On Carbon), which is believed to minimize the thermal loads because its cross-linker works at low temperature. Also, it would be important to fulfill the needs for the other properties of SOC like filling ability and etching resistance. So, we verified all these basic characteristics with proper resist and etching processes by getting good final pattern profile. As a result, LT-SOC is suggested for etching barrier without affecting on cell operation of memory devices.
As pattern design rule of device shrinks, CD control becomes more critical and important especially for resistance devices. As CD (Critical Dimension) increases, CDU (Critical Dimension Uniformity) becomes worse generally. The question with this relationship is a starting point of our study. Mainly we focused on two points. One is which factor affects CDU. The other is whether CDU degradation with large CD happens at all cases or not. We have analyzed with simulation and experiment results about CDU with splitted mask layout CD under limited conditions such as same equipment, illumination and exposure dose. As a result, we will show the relationship between CD size and CDU.