The next generation technology and emerging memory devices require gradually tighter lithographic focus control on imaging critical layers. Especially in case of BEOL process, big PDO (Process Dependent Offset) from large intra-field topography steps affects the process margin directly. There are couple of scanner options to reduce PDO, such as AGILE which provides several benefits. However, for certain use cases the AGILE sensor may not be the optimal solution.
In this paper, we introduce the concept and development background of iFPC (intra-field Finger Print Correction). iFPC is a scanner option that removes the generic 3D fingerprint seen in the leveling data so that both process dependency and actual wafer topography are not followed during wafer exposure.
In addition, we compare the degree of process margin improvement when applying iFPC compared to that of AGILE on a critical layer. The achieved results demonstrate that by applying iFPC it is possible to gain an additional 15~20nm DoF. In other words, on this use case our feasibility suggests that by removing the generic 3D fingerprint seen in the leveling data, it is possible to achieve a better focus performance than when trying to follow the topography during scanning.
In conclusion, we found another good way to improve the process margin through this comparative experiment. Therefore, our next step will be to setup the methodology to select the use cases where iFPC is the optimal solution.
ASML’s 300mm scanner-systems are built on the TWINSCAN (XT/NXT) platform and yield high productivity levels for dry as well as immersion litho-scanners. NXT:1980Di immersion scanners yield productivity levels as high as 275wph while maintaining the overlay accuracy. The NXT:1980Di can be equipped with a new leveling mode that results in a significant reduction of the time that is spent on measuring the wafer focus height map. In the new leveling mode the focus height map is measured employing the full width of the level sensor and thereby minimizing the number of leveling scans. In this paper we describe the implementation of the LIL-method in the TWINSCAN platform design. Here, we report on the focus / leveling performance for both test as well as customer product wafers, and present a productivity outlook on the performance gain for a selected set of exposure use-cases.
Scanners in High-Volume-Manufacturing conditions will experience a large range of reticles that vary in reticle transmission and reticle diffraction characteristics. Especially under full production loads reticles will heat up due to the exposure light-load and as such experience thermo-mechanical deformations. The resulting reticle pattern distortion can be partially translated in a deteriorated overall system overlay. Due to the geometry of the reticle and exposure fields, these reticle thermal effects are in general barrel-shape distortions that can be well corrected with the available set of lens manipulators. Nevertheless node-over-node the residual overlay errors associated with thermo-mechanical reticle deformation needs further reduction since it contributes to the total onproduct overlay performance. To reduce overlay caused by reticle temperature drift, NXT1980Di includes an active cooling mechanism suppressing the reticle temperature changes during exposure significantly. Even though the reticle temperature excursions are well suppressed, residual intra-wafer overlay drift effect can still be observed. Before exposure of a wafer, reticle deformation is measured during reticle align using in-line alignment / image sensors (TIS or PARIS). This is enabled by adding alignment markers around the circumference of the image field on the reticle. The measured reticle deformations are then fed to the system control network and dynamically corrected for by making use of the available manipulators in the scanner and the projection lens. Wafer-by-wafer reticle distortion measurements are performed to accurately capture the transient dynamics present in reticle heating during normal production lots. A new version of Reticle Heating Feed-forward Control (RHC2) is introduced that uses reticle-heating-induced deformation measurements over time and exposure sequence information to calibrate reticle-deformation-predictionmodels. These models are based on thermo-mechanical models that simulate reticle deformation under various exposure conditions and are applied in-line to the exposures to reduce intra-wafer overlay drift effects.
Shrinking pattern sizes dictate that scanner-to-scanner variations for HVM products shrink proportionally. This paper shows the ability to identify (a subset of) root causes for mismatch between ArF immersion scanners using scanner metrology. The root cause identification was done in a Samsung HVM factory using a methodology (Proximity Matching Budget Breakdown or PromaBB) developed by ASML. The proper identification of root causes-1 helps to select what combination of scanner control parameters should be used to reduce proximity differences of critical patterns while minimizing undesirable side effects from cross-compensation. Using PromaBB, the difference between predicted and measured CD mismatch was below 0.2nm. PromaBB has been proposed for HVM implementation at Samsung in combination with other ASML fab applications: Pattern Matcher Full Chip (PMFC), Image Tuner and FlexWave.
Overlay is one of the key factors which enables optical lithography extension to 1X node DRAM manufacturing. It is natural that accurate wafer alignment is a prerequisite for good device overlay. However, alignment failures or misalignments are commonly observed in a fab. There are many factors which could induce alignment problems. Low alignment signal contrast is one of the main issues. Alignment signal contrast can be degraded by opaque stack materials or by alignment mark degradation due to processes like CMP. This issue can be compounded by mark sub-segmentation from design rules in combination with double or quadruple spacer process. Alignment signal contrast can be improved by applying new material or process optimization, which sometimes lead to the addition of another process-step with higher costs. If we can amplify the signal components containing the position information and reduce other unwanted signal and background contributions then we can improve alignment performance without process change. In this paper we use ASML's new alignment sensor (as was introduced and released on the NXT:1980Di) and sample wafers with special stacks which can induce poor alignment signal to demonstrate alignment and overlay improvement.
As overlay margin is getting tighter, traditional overlay correction method is not enough to secure more overlay margin without extended correction potential on lithography tool. Timely, the lithography tool has a capability of wafer to wafer correction. From these well-timed industry’s preparations, the uncorrected overlay error from current sampling in a lot could be corrected for yield enhancement.
In this paper, overlay budget break was performed prior to experiments with the purpose of estimating amount of overlay improvement. And wafer to wafer correction was simulated to the specified layer of a 2x node DRAM device. As a result, not only maximum 94.4% of residual variation improvement is estimated, but also recognized that more samplings to cover all wafer’s behavior is inevitable. Integrated metrology with optimized sampling scheme was also introduced as a supportive method for more samplings.
Adjustment and control of the illumination pupil asymmetry is relevant for wafer alignment and overlay of lithography tools. Pupil asymmetries can cause a tilt in aerial image (Aerial Image Tilt, or AIT). This AIT, combined with a focus offset, leads to a horizontal image shift. Pupil asymmetries can be related to a shift of the entire illumination pupil (geometrical telecentricity) caused by illuminator misalign. Another type of pupil asymmetry is energetic imbalance (quantified by pupil Center of Gravity, COG). The scanner can show pupil variation across the exposure slit.
In general the COG at the edge of the slit is often worse than in the center part of the slit. Recently, ASML has released the NXT:1980Di that is equipped with an enhanced illuminator to improve pupil COG variation across the slit. In this paper we explore the performance of this scanner system and show that the AIT variation across the slit is also reduced significantly.
For mass production of DRAM device, a stable and effective overlay control becomes more and more important as DRAM design rule shrinks. Existent technologies were already applied to overcome this situation. Nevertheless, we are still suffered from tight overlay margin and forced to move from lot-based to wafer-based overlay control. However, the wafer-based control method requires a huge amount of measurement resource.
In this paper, we present the insight for the wafer-based overlay correction with optimal measurement resource which is suitable for mass production. The experiment which is the wafer-based overlay correction by several statistical analyses carried out for 2X nm node DRAM. Among them, linear regression is a strong candidate for wafer-based overlay control, which improved up to 0.8 nm of maximum overlay.
To accord with new requirement of securing more overlay margin, not only the optical overlay measurement is faced with the technical limitations to represent cell pattern’s behavior, but also the larger measurement samples are inevitable for minimizing statistical errors and better estimation of circumstance in a lot. From these reasons, diffraction based overlay (DBO) and integrated metrology (IM) were mainly proposed as new approaches for overlay enhancement in this paper.