As the design node of memory device shrinks, OPC model accuracy is becoming ever more critical from development to manufacturing. To improve the model accuracy, more and more physical effects are analyzed and terms for those physical effects are added. But it is unachievable to capture the complete physical effects. In this study, deep neural network is employed and studied to improve model accuracy. Regularization is achieved using physical guidance model. To address overfitting issue, high volume of contour based edge placement (EP) gauges (>10K) are generated using fast eBeam tool (eP5) and metrology processing software (MXP) without increasing turnaround time. It is shown that the new approach improved model accuracy by >47% compared to traditional approach on >1.4K verification gauges.
Traditional rule-based and model-based OPC methods only simulate in a very local area (generally less than 1um) to identify and correct for systematic optical or process problems. Despite this limitation, however, these methods have been very successful for many technology generations and have been a major reason for the industry being able to tremendously push down lithographic K1. This is also enabled by overall good across-exposure field lithographic process control which has been able to minimize longer range effects across the field. Now, however, the situation has now become more complex. The lithographic single exposure resolution limit with 1.35NA tools remains about 80nm pitch but the final wafer dimensions and final wafer pitches required in advanced technologies continue to scale down. This is putting severe strain on lithographic process and OPC CD control. Therefore, formerly less important 2nd order effects are now starting to have significant CD control impact if not corrected for. In this paper, we provide examples and discussion of how optical and chemical flare related effects are becoming more problematic, especially at the boundaries of large, dense memory arrays. We then introduce a practical correction method for these systematic effects which reuses some of the recent long range effect correcting OPC techniques developed for EUV pattern correction (such as EUV flare). We next provide analysis of the benefits of these OPC methods for chemical flare issues in 193nm lithography very low K1 lithography. Finally, we summarize our work and briefly mention possible future extensions.
The study of OPC (Optical Proximity Correction) model that well predict the wafer result has been
researched. As the pattern design shrink down, the need for the CD (Critical Dimension) controllability
increased more than before. To achieve these requirements, OPC models must be accurate for full chip
process and model inaccuracies are one of several factors which contribute to errors in the final wafer image.
For that reason, robust OPC using real lithographic terms was proposed. Real lithographic system is quite
different from ideal system that is used for OPC modeling. Until now, this difference was acceptable since
pattern size used for OPC model was large, but as device size shrinks, this gap between ideal and real system
causes degradation of OPC accuracy. So, various optical parameters such as apodization, laser band width,
degree of polarization, illumination are used today in order to compensate for this issue. Especially, major
issue in modeling error is related to how the illumination source is used. For this study we assess accuracy of optical model for robust OPC using ideal and actual illumination
sources, and test conditions are as follows: 1) We examined the difference of pupil types to output model respectively; 2) A parameterized test pattern layout was used by 1D test pattern types that have various lines and spaces; 3) All models were calculated in automation method so as to exclude the dependency of user skills; 4) OPC accuracies were examined by gate layer patterns on full chip level. The study is performed for 5X~4Xnm nodes lithographic processes. The main focus of the study was on usability of model that is made by measured source data in semiconductor manufacturing. Results clearly showed that the actual source for the optical model has merits and demerits.
In terms of mass production, the CD variation between exposure tools is not avoidable because of different exposure tool characteristics. The major CD variation is coming from different optical proximity effect (OPE) response between exposure tools. Knowing and control the major contributor to the OPE, ramping up the device will be faster because of one reticle usage in various exposure tools. Therefore, the quantitative measurement and simulation with actual exposure tool characteristics need for analyzing proximity impact to CD. For this purpose, collecting CD data on the wafers and analyzing was carried out to find large ID bias exposure tool. Normal and abnormal exposure tool in terms of proximity matching is inspected using LITEL products of ISI<sup>TM</sup>(In-situ Interferometer) and SMI<sup>TM</sup>(Source Metrology Interferometer). ISI<sup>TM</sup> and SMI<sup>TM</sup> were for collecting machine characteristic and Solid-E<sup>TM</sup> was for simulation purposes. From this study, the practical procedure is proposed to prevent using of large proximity exposure tool for production line and the impact of actual tools characteristic on proximity matching is known.
Polarization is becoming very important technology in micro-lithography at the higher NA lithography for much smaller design. The wide and intensive studies to apply the polarization technology into lithography application have been achieved. Source polarization, mask polarization and projection lens polarization could make different printing results compared to non-polarization cases. Especially k1 factor below 0.3 needs aggressive resolution enhancement techniques. Environmental parameters such as mask CD, lens aberration, stray light, image plane deviation and resist characteristic make CD controllability worse in the very low k1 regime. The polarization technology can contribute to getting better imaging performance. This experiment is challenging k1 factor down to 0.29 with the source polarization function. The source polarization effect on real device will be shown through the simulation and actual printing process using 6% attenuated PSM. The related OPC strategy with the polarized source will also be discussed.
As the minimum feature size shrinks down, i.e. low K1 lithography regime, the tool’s lens aberration sensitivity and user defined illumination imperfection might play a major role in patterning error. Thus, the study of impact from lens aberration and illumination on patterning is required for good tool maintenance and yield improvement. For this purpose, we collected many cases of abnormal patterning result from production line and then simulated in terms of actual lens aberration and illumination source data. LITEL products of ISI(In-situ Interferometer) and SMI(Source Metrology Interferometer) were used for characterizing lens and illumination source. Moreover, the ACE(Analysis and Characteristic Engine) of LITEL development product was used as the simulator.
In this work, deformation of pattern fidelity, for example, CD asymmetry in word line and metal contact layer, pattern bending in isolation layer and also decreasing process window in bit line layer will be discussed with experimental and simulation data. Finally, we are able to make a guideline for preventing abnormal phenomenon. From this study, we can understand which lens aberration terms and illumination imperfection take an effect of abnormal pattering result.