Reducing the overlay error between stacked layers is key to enabling higher pattern density and thus moving towards high performance and more cost effective devices. However, as for specific applications like macrochips with photonic interconnects and high-resolution image sensor flat panels with advance polarizers, customers require product field sizes that are larger than the maximum field size available on scanners. Those large fields are obtained by stitching together multiple standard fields. The overlay performances between two adjacent dies are as aggressive as what is usually required between two stacked layers. For this application, the well-established polynomial overlay model is not suitable as the displacement is measured relatively and the metrology sampling in the field is such that some high order nonlinear (K) terms cannot be modeled independently. Furthermore, a perfect grid is needed in mix and match production. The intrafield correction capability of the exposure tool is not the same for each process steps. For example, no intrinsic K13 can be printed for a mix and match process flow that includes an Extreme Ultra-Violet (EUV) litho step. In addition, some KrF scanners with fewer lens manipulators cannot correct for K9. Measuring the stitching and correcting it at the first layer will prevent printing K terms that are not correctable later in the process. In this paper, the need to characterize and control single-layer overlay among different pattern placement mechanisms intrinsic to the scanner was studied: optical aberrations, field-to-field position, mask placement and registration. An ASML set-up BP-XY-V3 reticle was used to generate a large experimental dataset to validate stitching models supported by Overlay Optimizer (OVO). Overlay measurements were done Resist-in-Resist using new YieldStar (YS) interlaced stitching Diffraction Based Overlay (μDBO) targets that were designed and validated. This paper will present on product metrology results of a scatterometry-based platform showing production results with focus not only on precision and on accuracy, but also assessing target performance and target-to-target delta without process influence. A high order stitching model was developed and verified on a Multi-Product Reticle for a large device application. Trench width control at the field intersection was studied then optimized with proximity correction to ensure a perfect field-to-field junction.
With these proceedings we present μ-diffraction-based overlay (μDBO) targets that are well below the currently supported minimum size of 10×10 μm2 . We have been capable of measuring overlay targets as small as 4×4 μm2 with our latest generation YieldStar system. Furthermore we find an excellent precision (TMU < 0.33 nm for 6 × 6 μm2 ) without any compromise on throughput (MAM time < 60 ms). At last a study that compares four generations of YieldStar systems show clearly that the latest generation YieldStar systems is much better capable of reading small overlay targets such that the performance of a 16 × 16 μm2 on an early generation YieldStar 2nd-gen is comparable to that of a 8 × 8 μm2 on the latest YieldStar 5th-gen. This work enables a smaller metrology footprint, more placement flexibility and in-die overlay metrology solutions.
Proc. SPIE. 10145, Metrology, Inspection, and Process Control for Microlithography XXXI
KEYWORDS: Target detection, Semiconductors, Lithography, Diffraction, Metrology, Polarization, Etching, Materials processing, Scanning electron microscopy, Scatterometry, Time metrology, Data processing, Process control, Target acquisition, Commercial off the shelf technology, Overlay metrology
Continuous tightening of the overlay control budget in the semiconductor industry drives the need for improved overlay metrology capabilities. In this context, measurement accuracy needs to be addressed. The first part this study shows that Diffraction Based Overlay metrology accuracy can be improved with a dedicated methodology. This methodology involves the use of target design simulation software in order to maximize stack sensitivity and to minimize processes non uniformity impact on the measurement. In the second part this study focuses on Holistic Metrology Qualification (HMQ) methodology that allows selecting the best on-wafer target. The methodology is explained and discussed. It is demonstrated that HMQ helps to reduce target asymmetry impact on measurement uncertainty and to select primary recipe parameters (wavelength, polarization, etc…). Finally CD-SEM measurements were used to validate methodology results.
Scatterometry mark design for improvement of the metrology performance is investigated in this joint work by
ASML and STMicroelectronics. The studied marks are small, enabling metrology within the device area. The new
mark-design approach reduces the effects from the mark-edges during the metrology measurement. For this, small
assist-features are integrated in the mark design on the wafer. Thereby the new designs: 1. enlarge the metrology
measurement-window, 2. optimize the repeatability and accuracy of the metrology at given mark size, 3. allow
added functionality to existing marks within the current mark area, such as monitoring process asymmetry or
multiple layer information, 4. allow for mark miniaturization at equal performance, enabling intra-field positioning.
With this metrology tool-optical proximity correction (MT-OPC) included in the mark design, the metrology window
is enhanced, while improved on-product overlay performance is obtained.
Continued tightening of overlay control budget in semiconductor lithography drives the need for improved metrology capabilities. Aggressive improvements are needed for overlay metrology speed, accuracy and precision. This paper is dealing with the on product metrology results of a scatterometry based platform showing excellent production results on resolution, precision, and tool matching for overlay. We will demonstrate point to point matching between tool generations as well as between target sizes and types. Nowadays, for the advanced process nodes a lot of information is needed (Higher order process correction, Reticle fingerprint, wafer edge effects) to quantify process overlay. For that purpose various overlay sampling schemes are evaluated: ultra- dense, dense and production type. We will show DBO results from multiple target type and shape for on product overlay control for current and future node down to at least 14 nm node. As overlay requirements drive metrology needs, we will evaluate if the new metrology platform meets the overlay requirements.
There are many IC-manufacturers over the world that use various exposure systems and
work with very high requirements in order to establish and maintain stable lithographic
processes of 65 nm, 45 nm and below. Once the process is established, manufacturer
desires to be able to run it on different tools that are available. This is why the proximity
matching plays a key role to maximize tools utilization in terms of productivity for
different types of exposure tools.
In this paper, we investigate the source of errors that cause optical proximity mismatch
and evaluate several approaches for proximity matching of different types of 193 nm
and 248 nm scanner systems such as set-get sigma calibration, contrast adjustment, and,
finally, tuning imaging parameters by optimization with Manual Scanner Matcher.
First, to monitor the proximity mismatch, we collect CD measurement data for the
reference tool and for the tool-to-be-matched. Normally, the measurement is performed
for a set of line or space through pitch structures.
Secondly, by simulation or experiment, we determine the sensitivity of the critical
structures with respect to small adjustment of exposure settings such as NA, sigma
inner, sigma outer, dose, focus scan range etc. that are called 'proximity tuning knobs'.
Then, with the help of special optimization software, we compute the proximity knob
adjustment that has to be applied to the tool-to-be-matched to match the reference tool.
Finally, we verify successful matching by exposing on the tool-to-be-matched with
tuned exposure settings.
This procedure is applicable for inter- and intra scanner type matching, but possibly
also for process transfers to the design targets.
In order to illustrate the approach we show experimental data as well as results of
imaging simulations. The set demonstrate successful matching of critical structures for
ArF scanners of different tool generations.
In this paper alignment and overlay results of the advanced technology nodes are presented. These results were obtained
on specially generated wafers as well as on regular manufacturing-type wafers. For this purpose, a new alignment sensor
was integrated and evaluated in three generations of lithography tools, placed in R&D and mass manufacturing facilities.
The capability of the sensor to align on marks with varying layout was evaluated. Long term overlay stability less than
11 nm was obtained on two different mark types: a standard ASML calibration mark and a flexible Toshiba mark design.
The ability to align on low-contrast marks was validated by a dedicated experiment: typical alignment repeatability
values of ~1 nm (3sigma) on shallow etch depth mark features of 25 nm are obtained for various mark designs, including
flexible pitch alignment marks. From these results, design directions for improved mark detect ability were defined. The
jointly developed mark designs were validated for their alignment robustness by an evaluation of manufacturing wafer
alignment performance. On-product overlay results on manufacturing wafers were measured for three different process
layers of the current technology node. The used alignment strategies were based on new mark capture and fine wafer
alignment mark designs, thereby making optimal use of the mark design flexibility potential of the alignment sensor.
Typical on-product overlay values obtained were less than 17 nm for the Active Area process layer, less than 12 nm for
the Gate Conductor process layer, and less than 19 nm for the Metal-1 process layer; after applying batch corrections, as
determined on a set of 2 send-ahead wafers. All results are based on full batch readout on an offline metrology tool. By
applying optimal batch process corrections for linear terms, typical overlay values range between 10-14 nm, depending
on the layer measured. Finally the sensor's infrared wavelengths were used to demonstrate a robust alignment solution
for wafers containing a semi-transparent hard-mask layer.
The greatest challenge for 65-nm contact holes and via printing is ensuring an acceptable process window (250-nm DoF @ 8% EL) for a wide range of pitches with a MEEF lower than 3.5. To print dense contact holes / vias with a CD less than 100-nm, very high Numerical Apertures (≥ 0.85) are required. Consequently DoF through pitch is dramatically reduced, such that it becomes absolutely necessary to develop new techniques to enhance process latitude. In this paper, we will study the use of customized illuminations formed by combination of small radius conventional illumination and quasar. Generically, this type of illumination is commonly referred to as 5-pole illumination. Specifically this paper, the “windmill” and “soft quasar” options are investigated. These designs are based upon the assumption, that there is a way to optimize for all pitches, the imaging lens pupil filling with diffracted orders. Using a combination of aerial image simulations and experimental (double) exposures, the optimal 5-pole illumination designs are derived, with their simulated performance being compared to conventional illumination settings. For the optimised designs, experimental data is presented for “real” device structures based on the Crolles2 65-nm technology design rules.
In this paper, methods for stacking ASML scribe lane alignment marks (SPM) and improving the mark performance at initial copper metal levels are discussed. The new mark designs and the theoretical reasons for mark design and/or integration change are presented. In previous joint publications between ASML and Freescale Semiconductor , improved overlay performance and alignment robustness for Back End Of Line (BEOL) layers by the application of stacked scribe lane marks (SPM) was presented. In this paper, further improvements are demonstrated through the use of optimized Versatile Scribe Lane Mark design (VSPM). With the application of stacked optimized VSPM-marks, the alignment signal strength of marks in the copper metal layer is increased compared to stacked SPM marks. The gains in signal strength stability, which is typical for stacked marks, as well as significantly reduced scribe lane usage, are also maintained. Through the placement of specially designed orthogonal scatter-bars in selected layers under the VSPM-marks, the alignment performance of initial inlaid metal layers is improved as well. The integration of these marks has been evaluated for the 90 nm and 65 nm technology nodes as part of a joint development program between the Crolles2 Alliance and ASML. A measured overlay improvement of ~10-15% was obtained by a strategy change from floating copper marks to stacked optimized VSPM marks.
Quality of exposures on Step&Scan systems highly depends on stages synchronization. While scanning, wafer and reticle stages must have same relative speed (4x ratio) and directions. In this paper, we investigate the tolerance to lateral vibrations of 0.18micrometers and 0.12micrometers gate patterning respectively on an ASML PAS5500/750E scanner (KrF) and a PAS5500/900 scanner (ArF) exposure tools. Results should be given both on the MA impact on overlay and the MSD effect on CD control. But, as no adapted experimental method has been found to correlate overlay degradation to induced MA and then confirm the theory that 1nm of MA induces 1nm of translation, only results on CD control will be discussed, including lateral MSD impact on nominal CD variations, process latitudes degradations and intrafield CD dispersion. In particular, we will show that MSD effect on CD strongly differs from 248nm imaging process to 193nm one.