The utilization of a cut-mask in semiconductor patterning processes has been in practice for logic devices since the inception of 32nm-node devices, notably with unidirectional gate level printing. However, the microprocessor applications where cut-mask patterning methods are used are expanding as Self-Aligned Double Patterning (SADP) processes become mainstream for 22/14nm fin diffusion, and sub-14nm metal levels. One common weakness for these types of lithography processes is that the initial pattern requiring the follow-up cut-mask typically uses an extreme off-axis imaging source such as dipole to enhance the resolution and line-width roughness (LWR) for critical dense patterns. This source condition suffers from poor process margin in the semi-dense (forbidden pitch) realm and wrong-way directional design spaces. Common pattern failures in these limited design regions include bridging and extra-printing defects that are difficult to resolve with traditional mask improvement means. This forces the device maker to limit the allowable geometries that a designer may use on a device layer.
This paper will demonstrate methods to expand the usable design space on dipole-like processes such as unidirectional gate and SADP processes by utilizing the follow-up cut mask to improve the process window. Traditional mask enhancement means for improving the process window in this design realm will be compared to this new cut-mask approach. The unique advantages and disadvantages of the cut-mask solution will be discussed in contrast to those customary methods.
EUV is an ongoing industry challenge to adopt due to its current throughput limitations. The approach to improve
throughput has primarily been through a significant focus on source power which has been a continuing challenge
for the industry. The subject of this paper is to review and investigate the application of SADP (Self aligned double
patterning) as a speed enhancing technique for EUV processing. A process with the potential of running a 16 nm
self-aligned final etched pattern in less than 10mJ exposure range is proposed. Many of the current challenges with
shot noise and resolution change significantly when SADP is used in conjunction with EUV. In particular, the
resolution challenge for a 16nm HP final pattern type image changes to 32nm as an initial pattern requirement for
the patterned CD.
With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed
resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements
for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry
where the relaxation of both LER and CD together combined, give the resist formulation space a new target when
EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final
16nm half pitch target pattern to align with the industry needs.
If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow
proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed
process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added
costs associated with the double patterning process. This flow can then be shown to be an enabling approach for
many EUV applications.