In advanced semiconductor industries, the overlay error budget is getting tighter due to shrinkage in technology. To
fulfill the tighter overlay requirements, gaining every nanometer of improved overlay is very important in order to
accelerate yield in high-volume manufacturing (HVM) fabs. To meet the stringent overlay requirements and to overcome
other unforeseen situations, it is becoming critical to eliminate the smallest imperfections in the metrology targets used
for overlay metrology. For standard cases, the overlay metrology recipe is selected based on total measurement
uncertainty (TMU). However, under certain circumstances, inaccuracy due to target imperfections can become the
dominant contributor to the metrology uncertainty and cannot be detected and quantified by the standard TMU. For
optical-based overlay (OBO) metrology targets, mark asymmetry is a common issue which can cause measurement
inaccuracy, and it is not captured by standard TMU.
In this paper, a new calibration method, Archer Self-Calibration (ASC), has been established successfully in HVM fabs
to improve overlay accuracy on image-based overlay (IBO) metrology targets. Additionally, a new color selection
methodology has been developed for the overlay metrology recipe as part of this calibration method. In this study,
Qmerit-calibrated data has been used for run-to-run control loop at multiple devices. This study shows that color filter
can be chosen more precisely with the help of Qmerit data. Overlay stability improved by 10~20% with best color
selection, without causing any negative impact to the products. Residual error, as well as overlay mean plus 3-sigma,
showed an improvement of up to 20% when Qmerit-calibrated data was used. A 30% improvement was seen in certain
electrical data associated with tested process layers.
Shrinking semiconductor device nodes are driving continuous overlay improvement. This, in turn, is driving broad adoption of high-order control, especially at today’s advanced nodes. There are two main categories of high-order control: wafer alignment, and process correction. This paper focuses on the inherent disadvantages of high-order process correction models due to data noise and the deterioration of model term stability. In our study, we observed that linear model terms became unstable after the implementation of high-order process corrections, and observed correlations between model parameters. We investigated correlations for both linear and high-order models, and found that all correlation combinations for the linear model had a Pearson correlation coefficient below 0.25, while 22% of the correlation combinations for third order polynomial parameters had a correlation coefficient greater than 0.5. A high correlation coefficient indicates that similar overlay signatures on the wafer can be modeled by different terms, and that there is instability of model terms in the presence of data noise. Advanced process control (APC) corrections are based on historical lot-to-lot model terms, and are applied to each new lot to be exposed. The instability of model terms adversely affects the precise prediction for a new lot. An alternative solution is to use cascading analysis, which calculates the model parameters sequentially using a series of models. The inherent disadvantage of cascading analysis is loss of model fidelity; however, the robust data filtering scheme used in cascading analysis ensures better overlay stability, as shown in the results of this study. This study shows that cascading analysis consistently yields a lower correlation within and across a batch of lots, but with improved overlay control. Several methods of cascading analysis were investigated in terms of the sequence of linear and high-order modeling. This was done to determine the optimal method for implementing cascading analysis, and to determine the implications of cascading analysis in today’s high-volume mass production fabrication facility.