A comparison is presented for three different feedback signal shapes on a current mode continuous-time second order sigma-delta modulator, although, it can be extended to systems of any order. The three shapes are: rectangular, exponential, and a new mixed waveform whose pulse starts being rectangular and after a fraction of the clock period changes to decaying ramp. Simulation results at system level, using a software model, are presented. Results show that using early return to zero feedback signal shapes (exponential, mixed) the modulator performance degradation due to pulse width variation is reduced with respect to rectangular signal shapes. In addition to that, the new mixed shaped do not present the high signal peak that the exponential does. This is important from the point of view of integrator input stage because it allows power saving as well as critical input noise reduction.
In this work a dual-mode complex multibit continuous-time ΔΣ modulator for a standard 0.25<i>μm</i> CMOS technology is presented. This modulator is intended for the analog-to-digital conversion in multi-mode wireless-LAN receivers (802.11a/b/g) which require wide bandwidth and moderate resolution. Then, a low oversampling ratio of 16 along with a clock frequency of 320 MHz provides a signal bandwidth of 20 MHz for a 9-bit resolution with a second-order modulator. The modulator can be configured for two different modes of operation depending on the type of radio receiver chosen: "zero-IF" (ZIF) and "low-IF" (LIF). The former mode is better suited for 802.11b, while LIF mode is more adequate for 802.11a/g applications. The loop filter is based on transconductors and MOS-capacitors allowing for low power consumption and small chip area. The modulator also includes two 3-bit quantizers, both with their corresponding DWA scrambler. The supply voltage is 2.5V and the measured power consumption is 32 mW. Experimental results using both sine-wave and OFDM signals are presented. The obtained SNR and SNDR are 55dB and 53.5dB, respectively. A high image rejection of 47dB is achieved owing to proper layout techniques. When using OFDM signals, a minimum error vector magnitude of 1.3% is obtained. Finally, the active chip area is 0.44<i>mm</i><sup>2</sup> .