Silicon weak pattern exploration becomes more and more attractive for yield improvement and design robustness as these proven silicon weak patterns or hotspots directly reveals process weakness and should be avoided to occur on the chip design. At the very beginning, only a few known hotspot patterns are available as seeds to initialize the weak pattern accumulation process. Machine learning technique can be utilized to expand the weak pattern database, the data volume is critical for machine learning. Fuzzy patterns are built and more potential hotspots locations are found and sent to YE team to confirm, thus more silicon proven data is available for machine learning model training, both good patterns and bad patterns are valuable for the training data set. The trained machine learning model is then used for new hotspots prediction. The outcome from the machine learning prediction need to be validated by silicon data in the first few iterations. When a reliable machine learning model is ready for hotspots detection, designers can run hotspot prediction at the design stage. There are some techniques in training the mode and will be discussed in details in the paper.
It’s desirable to gain high yield and good performance for memory products. Designers have to do some advanced DFM checking on their designs and fix all the critical design issues to be correct by construction before manufacturing. One of the DFM checking items is the litho hotspot checking, LFD (Litho Friendly Design) is the tool adopted for that checking due to its user friendly interface for designers and being able to be integrated with other tools for the advanced checking flow development. One challenge to enable this checking as the signoff item is the long runtime due to the computing-intensive litho simulation. Multiple ways have been figured out to reduce the runtime, for instance, hierarchical checking flow similar to hierarchical design flow under the assumption that many design blocks are reused on the top level; simulation only on the area selected by weak pattern candidates stored in a pattern matching library; simulation only on the unique pattern area by firstly decomposing the layout. All these approaches always tradeoff between runtime and simulation accuracy and come to use with different expectations as the process gradually matures. This paper introduces another technique to reduce the simulation time. This technique is essentially a pattern matching extended application and will be introduced in detail in the paper.
Proc. SPIE. 10962, Design-Process-Technology Co-optimization for Manufacturability XIII
KEYWORDS: Data modeling, Copper, Manufacturing, Chemical vapor deposition, 3D modeling, Semiconducting wafers, Process modeling, Chemical mechanical planarization, Back end of line, Design for manufacturability
Vertical NAND (3D NAND) designs provide unprecedented improvements in input/output (I/O) performance and storage density, but require additional analysis to ensure manufacturing and market success. While 3D stacked architectures greatly reduce chip area at advanced technology nodes, greater topology uniformity is essential, not only for inter-layers stacking, but also for the chip bonding process. As the link between design and manufacturing, design for manufacturing (DFM) predicts potential manufacturing issues during the design stage, enabling design teams to modify the layout and mitigate the risk. The copper interconnect process can be modeled through multiple process steps, from film stacking, etch, and copper deposition to polishing. The simulated topology of a given design predicts potential risky areas that may be fixed by changing designs or inserting dummy fill prior to manufacturing. This simulation is a useful technique during yield ramp-up, and can shorten the cycle from design to manufacturing. This paper presents a solution for BEOL CMP modeling and analysis on BEOL copper interconnect of a 3D NAND flow.
Chemical-mechanical polishing (CMP) is a key process that reduces chip topography variation during manufacturing. Any variation outside of specifications can cause hotspots, which negatively impact yield. As technology moves forward, especially in memory processes like 3D NAND, high-quality surface planarity is required to overcome manufacturing challenges in each process step. Any topography variation in the front-end-of-line (FEOL) must be taken into consideration, as it may dramatically impact the surface planarity achieved by subsequent manufacturing steps. Rule-based checking of the design is not sufficient to discover all potential CMP hotspots. An accurate FEOL CMP model is necessary to predict design-induced CMP hotspots and optimize the use of dummy fill to alleviate manufacturing challenges. While back-end-of-line (BEOL) CMP modeling technology has matured in recent years, FEOL CMP modeling is still facing multiple challenges. This paper describes how an accurate FEOL CMP model may be built, and how interlayer dielectric (ILD) layer CMP simulations may be used for 3D NAND design improvement. In the example of ILD CMP model validation for a 3D NAND product, it is shown that the model predictions match well with the silicon data and that the model may successfully be used for hotspot prediction in production designs prior to manufacturing.